Method for opto-electronic integration on a SOI substrate and related structure
View Patent ↗According to an exemplary embodiment, a method includes providing a silicon-on-insulator substrate including a buried oxide layer situated over a bulk silicon substrate and a silicon layer situated over the buried oxide layer. A trench is formed in the silicon layer and the buried oxide layer, where the trench exposes a portion of the bulk silicon substrate, and where the trench is situated adjacent to an optical region of said silicon-on-insulator substrate. According to this exemplary embodiment, an epitaxial layer is formed on the exposed portion of the bulk silicon substrate in the trench. The epitaxial layer and the bulk silicon substrate form a bulk silicon electronic region of the silicon-on-insulator substrate.
1. A structure comprising:
a silicon-on-insulator substrate comprising a buried oxide layer having a first thickness situated over a bulk silicon substrate and a silicon layer having a second thickness situated over said buried oxide layer;
a trench situated in said silicon layer and said buried oxide layer, said trench having a first and a second sidewall, said trench being situated adjacent to an optical region of said silicon-on-insulator substrate, wherein said optical region comprises at least one optical component;
an epitaxial layer situated in said trench and situated on said bulk silicon substrate;
wherein said epitaxial layer and said bulk silicon substrate form a bulk silicon electronic region of said silicon-on-insulator substrate;
wherein said optical region of said silicon-on-insulator substrate is optimized for at least one optical component by controlling said first thickness of said buried oxide layer and said second thickness of said silicon layer.
2. The structure of claim 1 further comprising a first spacer and a second spacer, said first spacer being situated between said first sidewall of said trench and said epitaxial layer said second spacer being situated between said second sidewall of said trench and said epitaxial layer.
3. The structure of claim 1 further comprising an interlayer dielectric layer situated over said silicon-on-insulator substrate.
4. The structure of claim 3 further comprising a first interconnect metal segment and a second interconnect metal segment situated on said interlayer dielectric layer, said first interconnect metal segment connected to said optical region by a first contact and said second interconnect metal segment connected to said bulk silicon electronic region by a second contact.
5. The structure of claim 1 wherein said silicon-on-insulator substrate has a planar surface, said planar surface including a top surface of said silicon layer and a top surface of said epitaxial layer.
6. The structure of claim 2 further comprising a first conformal dielectric layer portion situated between said first spacer and said epitaxial layer and a second conformal dielectric layer portion situated between said second spacer and said epitaxial layer.
7. The structure of claim 1 wherein said trench has a depth of between approximately 1.5 microns and approximately 2.0 microns.
8. The structure of claim 1 wherein said second thickness of said silicon layer is between approximately 3000.0 Angstroms and approximately 6000.0 Angstroms.
9. The structure of claim 1 wherein said first thickness of said buried oxide layer is approximately 1.25 microns.