CMOS transistor spacers formed in a BiCMOS process
View Patent ↗According to an exemplary method in one embodiment, a transistor gate is fabricated on a substrate. Next, an etch stop layer may be deposited on the substrate. The etch stop layer may, for example, be TEOS silicon dioxide. Thereafter, a conformal layer is deposited over the substrate and the transistor gate. The conformal layer may, for example, be silicon nitride. An opening is then etched in the conformal layer. Next, a base layer is deposited on the conformal layer and in the opening. The base layer may, for example, be silicon-germanium. According to this exemplary embodiment, an emitter may be formed on the base layer in the opening. Next, the base layer is removed from the conformal layer. The conformal layer is then etched back to form a spacer adjacent to the transistor gate. In one embodiment, a structure is fabricated according to the above described exemplary method.
1. A structure comprising:
a transistor gate situated on a substrate;
a conformal layer situated on said substrate, said conformal layer covering said transistor gate and said conformal layer having an opening;
a base layer situated directly on said conformal layer and in said opening, wherein said base layer is situated over said transistor gate and on a top surface of a collector situated in said substrate;
wherein said conformal layer is utilized to form spacers adjacent to said transistor gate, and wherein said base layer is utilized to form a transistor base on said collector.
2. The structure of claim 1 further comprising an etch stop layer situated between said substrate and said conformal layer.
3. The structure of claim 2 wherein said etch stop layer comprises TEOS silicon dioxide.
4. The structure of claim 1 wherein said conformal layer comprises silicon nitride.
5. The structure of claim 1 wherein said base layer comprises silicon-germanium.
6. The structure of claim 1 wherein said transistor gate is a PFET gate.
7. A structure comprising:
a transistor gate situated on a substrate;
an etch stop layer situated on said substrate, said etch stop layer being in direct contract with said transistor gate;
a conformal layer situated in direct contact with said etch stop layer;
a base layer situated on said conformal layer and in an opening in said conformal layer and said etch stop layer;
wherein said conformal layer is utilized to form spacers adjacent to said transistor gate.
8. The structure of claim 7 further comprising an emitter situated on said base layer in said opening.
9. The structure of claim 7 wherein said etch stop layer comprises TEOS silicon dioxide.
10. The structure of claim 7 wherein said conformal layer comprises silicon nitride.
11. The structure of claim 7 wherein said base layer comprises silicon-germanium.
12. The structure of claim 7 wherein said transistor gate is a PFET gate.