IP Library Granted Patent US 7,033,898
Granted Patent B1
US 7,033,898 · App. 10/865,153 · Granted Apr 25, 2006

Method for fabricating a self-aligned bipolar transistor having recessed spacers

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Quick Facts
Patent No.
US 7,033,898
App. No.
10/865,153
Granted
Apr 25, 2006
Kind
B1
Abstract

According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a first link spacer and a second link spacer situated on the top surface of the base. The bipolar transistor further comprises a sacrificial post situated between the first and second link spacers, where the first and second link spacers have a height that is substantially less than a height of the sacrificial post. The bipolar transistor also comprises a conformal layer situated over the sacrificial post and the first and second link spacers. According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer, the first and second link spacers, the sacrificial post, and the base. The sacrificial planarizing layer may comprise, for example, an organic material such as an organic BARC (“bottom anti-reflective coating”).

Claims (13)

1. A method for fabricating a bipolar transistor, said method comprising steps of:

fabricating a sacrificial post on a top surface of a base of said bipolar transistor;

fabricating a first link spacer and a second link spacer on, respectively, a first side and a second side of said sacrificial post, said first and said second link spacers having a height substantially less than a height of said sacrificial post;

forming a conforming layer over said sacrificial post and over said first and said second link spacers;

depositing a sacrificial planarizing layer over said conformal layer, said sacrificial post, said first and said second link spacers, and said base of said bipolar transistor.

2. The method of claim 1 further comprising steps of:

depositing a mask over said sacrificial planarizing layer;

patterning an emitter window opening in said mask.

3. The method of claim 1 where said conformal layer is directly in contact with said first and said second sides of said sacrificial post.

4. The method of claim 1 wherein said sacrificial planarizing layer comprises an organic material.

5. The method of claim 4 wherein said organic material is an organic BARC.

6. The method of claim 1 wherein said sacrificial planarizing layer is deposited using a spin-on process.

7. The method of claim 1 further comprising a step of etching an emitter window opening in said sacrificial planarizing layer.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Oct 18, 2023
From: WELLS FARGO CAPITAL FINANCE, LLC, AS SUCCESSOR BY MERGER TO WACHOVIA CAPITAL FINANCE CORPORATION (WESTERN)
To: NEWPORT FAB, LLC DBA JAZZ SEMICONDUCTOR OPERATING COMPANY
Reel/Frame 065284/0123 →
FIRST AMENDMENT TO PATENT SECURITY AGREEMENT Recorded Apr 4, 2007
From: NEWPORT FAB, LLC
To: WACHOVIA CAPITAL FINANCE CORPORATION (WESTERN)
Reel/Frame 019111/0295 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 6, 2005
From: KALBURGE, AMOL; YIN, KEVIN Q.
To: NEWPORT FAB, LLC DBA JAZZ SEMICONDUCTOR
Reel/Frame 016650/0622 →