IP Library Granted Patent US 7,235,861
Granted Patent B1
US 7,235,861 · App. 11/003,572 · Granted Jun 26, 2007

NPN transistor having reduced extrinsic base resistance and improved manufacturability

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,235,861
App. No.
11/003,572
Granted
Jun 26, 2007
Kind
B1
Abstract

A method for fabricating an NPN bipolar transistor comprises forming a base layer on a top surface of a substrate. The NPN bipolar transistor may be an NPN silicon-germanium heterojunction bipolar transistor. The method for fabricating the NPN bipolar transistor may further comprise a cap layer situated over the base layer. According to this embodiment, the method for fabricating the NPN bipolar transistor further comprises fabricating an emitter over the base layer, where the emitter defines an intrinsic and an extrinsic base region of the base layer. The emitter may comprise, for example, polycrystalline silicon. The method for fabricating the NPN bipolar transistor further comprises implanting germanium in the extrinsic base region of the base layer so as to make the extrinsic base region substantially amorphous. The method for fabricating the NPN bipolar transistor further comprises implanting boron in the extrinsic base region of the base layer.

Claims (15)

1. An NPN bipolar transistor comprising:

a base layer situated over a collector, said base layer comprising an intrinsic base region and an extrinsic base region;

an emitter situated over said intrinsic base region of said base layer;

a cap layer situated over said base layer, said cap layer comprising polycrystalline silicon, said cap layer having a substantially amorphous portion situated over said extrinsic base region, said substantially amorphous portion of said cap layer comprising implanted germanium.

2. The NPN bipolar transistor of claim 1 wherein said base layer comprises silicon-germanium.

3. The NPN bipolar transistor of claim 1 wherein said emitter comprises polycrystalline silicon.

4. An NPN bipolar transistor comprising:

a buried layer formed in a substrate;

a collector situated over said buried layer;

a base layer situated over said collector, said base layer comprising an intrinsic base region and an extrinsic base region;

an emitter situated over said intrinsic base region of said base layer;

a cap layer comprising polycrystalline silicon situated over said base layer, said cap layer having a substantially amorphous portion situated over said extrinsic base region, said substantially amorphous portion of said cap layer comprising implanted germanium.

5. The NPN bipolar transistor of claim 4 wherein said base layer comprises silicon-germanium.

6. The NPN bipolar transistor of claim 4 wherein said emitter comprises polycrystalline silicon.

7. The NPN bipolar transistor of claim 4 wherein said collector comprises single crystal silicon.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Oct 18, 2023
From: WELLS FARGO CAPITAL FINANCE, LLC, AS SUCCESSOR BY MERGER TO WACHOVIA CAPITAL FINANCE CORPORATION (WESTERN)
To: NEWPORT FAB, LLC DBA JAZZ SEMICONDUCTOR OPERATING COMPANY
Reel/Frame 065284/0123 →
FIRST AMENDMENT TO PATENT SECURITY AGREEMENT Recorded Apr 4, 2007
From: NEWPORT FAB, LLC
To: WACHOVIA CAPITAL FINANCE CORPORATION (WESTERN)
Reel/Frame 019111/0295 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 9, 2005
From: HOWARD, DAVID; RACANELLI, MARCO; U'REN, GREG D.
To: NEWPORT FAB, LLC DBA JAZZ SEMICONDUCTOR
Reel/Frame 016670/0823 →