Method for fabricating a self-aligned bipolar transistor
View Patent ↗According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a sacrificial post which, in one exemplary embodiment, is situated between first and second link spacers. The bipolar transistor also comprises a conformal layer situated over the sacrificial post. The conformal layer may comprise silicon oxide, for example. According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer, the sacrificial post, and the base. The sacrificial planarizing layer has a first thickness in a first region between the first and second link spacers and a second thickness in a second region outside of the first and second link spacers, where the second thickness is generally greater than the first thickness. Another embodiment is a method that achieves the above-described bipolar transistor.
1. A method for fabricating a bipolar transistor, said method comprising steps of:
fabricating a sacrificial post on a top surface of a base;
forming a conforming layer over said sacrificial post;
depositing a sacrificial planarizing layer over said conformal layer, said sacrificial post, and said base;
wherein said sacrificial post is fabricated prior to formation of an emitter of said bipolar transistor.
2. The method of claim 1 further comprising a step of fabricating first and second link spacers on, respectively, first and second sides of said sacrificial post prior to said step of forming said conformal layer.
3. The method of claim 1 further comprising steps of:
depositing a mask over said sacrificial planarizing layer;
patterning an emitter window opening in said mask.
4. The method of claim 1 wherein said sacrificial planarizing layer comprises an organic material.
5. The method of claim 4 further comprising a step of removing said sacrificial planarizing layer by a process selected from the group consisting of a plasma etch and a sulfuric wet etch.
6. The method of claim 4 wherein said organic material is an organic BARC.
7. The method of claim 1 wherein said sacrificial planarizing layer is deposited using a spin-on process.
8. The method of claim 3 wherein said emitter window opening has a width greater than a width of said sacrificial post.
9. The method of claim 3 wherein said emitter window opening has a width smaller than a width of said sacrificial post.
10. The method of claim 3 wherein said emitter window opening has a width approximately equal to a width of said sacrificial post.
11. The method of claim 1 further comprising a step of etching an emitter window opening in said sacrificial planarizing layer.
12. The method of claim 1 wherein said bipolar transistor is a silicon-germanium heterojunction bipolar transistor.
13. The method of claim 1 wherein said bipolar transistor is a silicon-germanium-carbon heterojunction bipolar transistor.
14. A method for fabricating a bipolar transistor, said method comprising steps of:
fabricating a sacrificial post on a top surface of a base;
fabricating first and second link spacers on, respectively, first and second sides of said sacrificial;
forming a conforming layer over said sacrificial post and said first and second link spacers;
depositing a sacrificial planarizing layer over said conformal layer, said sacrificial post, said first and second link spacers, and said base.