Densely packed metal segments patterned in a semiconductor die
View Patent ↗A method of patterning a metal layer in a semiconductor die comprises forming a mask on the metal layer to define an open region and a dense region. The method further comprises etching the metal layer at a first etch rate to form a number of metal segments in the open region and etching the metal layer at a second etch rate to form a number of metal segments in the dense region, where the first etch rate is approximately equal to the second etch rate. The method further comprises performing a number of strip/passivate cycles to remove a polymer formed on sidewalls of the metal segments in the dense region. The sidewalls of the metal segments in the dense region undergo substantially no undercutting and residue is removed from the sidewalls of the metal segments in the dense region.
1. A structure in a semiconductor die, said structure comprising:
a first metal segment and a second metal segment situated on a dielectric layer, said first metal segment and said second metal segment being situated in an open region of said semiconductor die;
a third metal segment and a fourth metal segment situated on said dielectric layer, said third metal segment and said fourth metal segment being situated in a dense region of said semiconductor die, respective sidewalls of said third and said fourth metal segments comprising substantially no residue or polymer;
said first metal segment and said second metal segment being formed by etching a metal layer at a first etch rate, said third metal segment and said fourth metal segment being formed by etching said metal layer at a second etch rate, wherein said third and fourth metal segments are formed with substantially no sidewall undercutting by increasing an amount of an etch inhibitor such that said first etch rate is approximately equal to said second etch rate, wherein said etch inhibitor is selected from the group consisting of N2 and CHF3, wherein a spacing aspect ratio in said dense region is greater than 2.5, and wherein said dielectric layer between said third metal segment and said fourth metal segment is substantially co-planar with a bottom portion of said third metal segment and said fourth metal segment.
2. The structure of claim 1 wherein a spacing aspect ratio in said open region is substantially less than said spacing aspect ratio in said dense region.
3. The structure of claim 1 wherein a spacing aspect ratio in said open region is less than 2.0.
4. The structure of claim 1 wherein a thickness of said metal layer is greater than approximately 4.0 microns.
5. A structure in a semiconductor die, said structure comprising:
a first metal segment and a second metal segment situated on a dielectric layer, said first metal segment and said second metal segment being situated in an open region of said semiconductor die;
a third metal segment and a fourth metal segment situated on said dielectric layer, said third metal segment and said fourth metal segment being situated in a dense region of said semiconductor die, respective sidewalls of said third and said fourth metal segments comprising substantially no residue or polymer;
said first metal segment and said second metal segment being formed by etching a metal layer at a first etch rate, said third metal segment and said fourth metal segment being formed by etching said metal layer at a second etch rate, wherein said third and fourth metal segments are formed with substantially no sidewall undercutting by increasing an amount of an etch inhibitor such that said first etch rate is approximately equal to said second etch rate, wherein a spacing aspect ratio in said dense region is greater than 2.5, and said dielectric layer between said third metal segment and said fourth metal segment is substantially co-planar with a bottom portion of said third metal segment and said fourth metal segment.
6. The structure of claim 5 wherein a spacing aspect ratio in said open region is substantially less than said spacing aspect ratio in said dense region.
7. The structure of claim 5 wherein a spacing aspect ratio in said open region is less than 2.0.
8. The structure of claim 5 wherein a thickness of said metal layer is greater than approximately 4.0 microns.
9. A structure in a semiconductor die, said structure comprising:
a first metal segment and a second metal segment situated on a dielectric layer, said first metal segment and said second metal segment being situated in an open region of said semiconductor die;
a third metal segment and a fourth metal segment situated on said dielectric layer, said third metal segment and said fourth metal segment being situated in a dense region of said semiconductor die, respective walls of said third and said fourth metal segments comprising substantially no residue or polymer;
said first metal segment and said second metal segment being formed by etching a metal layer at a first etch rate, said third metal segment and said fourth metal segment being formed by etching said metal layer at a second etch rate, wherein said third and fourth metal segments are formed with substantially no sidewall undercutting by increasing an amount of an etch inhibitor such that said first etch rate is approximately equal to said second etch rate, wherein a spacing aspect ratio in said dense region is greater than 2.5, and wherein a thickness of said metal layer is greater than approximately 4.0 microns.
10. The structure of claim 9 wherein said spacing aspect ratio in said open region is substantially less than said spacing aspect ratio in said dense region.