Method for fabricating a top conductive layer in a semiconductor die and related structure
View Patent ↗According to an exemplary embodiment, a method for fabricating a top conductive layer in a semiconductor die includes forming a through-wafer via opening through at least one interlayer dielectric layer in a through-wafer via region of the semiconductor die. The method further includes extending the through-wafer via opening through a substrate of the semiconductor die to reach a target depth. The method further includes forming a through-wafer via conductive layer in the through-wafer via opening, and concurrently forming the top conductive layer over an exposed top metal segment.
1. A semiconductor die comprising at least one interlayer dielectric layer overlying a substrate, said semiconductor die further comprising:
a through-wafer via extending through said at least one interlayer dielectric layer and said substrate, said through-wafer via comprising a through-wafer via conductive layer, said through-wafer via conductive layer formed concurrently with a top conductive layer over a top metal segment and a passivation stack, said top metal segment and said passivation stack being situated over said at least one interlayer dielectric layer;
wherein said through-wafer via conductive layer is separated from said to conductive layer.
2. The semiconductor die of claim 1 further comprising a first frontside passivation segment situated over said through-wafer via conductive layer and a second frontside passivation segment situated over said top conductive layer.
3. The semiconductor die of claim 1 wherein said top conductive layer comprises a metal layer situated over an adhesion/barrier layer.
4. The semiconductor die of claim 1 wherein said semiconductor die is enclosed in a semiconductor package.
5. The semiconductor die of claim 1 wherein said passivation stack comprises an upper passivation layer situated over a lower passivation layer, wherein said upper passivation layer comprises polyimide.
6. The semiconductor die of claim 1 wherein said top conductive layer is part of an inductor residing on said semiconductor die.
7. The semiconductor die of claim 1 wherein said top conductive layer is utilized to route power in said semiconductor die.
8. The semiconductor die of claim 1 wherein said top conductive layer is utilized to route ground in said semiconductor die.
9. The semiconductor die of claim 1 wherein said substrate comprises silicon.
10. The semiconductor die of claim 1 wherein said substrate comprises gallium arsenide.
11. A semiconductor die comprising at least one interlayer dielectric layer overlying a substrate, said semiconductor die further comprising:
a through-wafer via extending through said at least one interlayer dielectric layer and said substrate;
said through-wafer via comprising a through-wafer via conductive layer, said through-wafer via conductive layer being formed concurrently with a top conductive layer over a top metal segment, said top metal segment being situated over said at least one interlayer dielectric layer;
wherein said through-wafer via conductive layer is separated from said top conductive layer.
12. The semiconductor die of claim 11 further comprising a first frontside passivation segment situated over said through-wafer via conductive layer.
13. The semiconductor die of claim 12 further comprising a second frontside passivation segment situated over said top conductive layer.
14. The semiconductor die of claim 11 wherein said top conductive layer comprises a metal layer situated over an adhesion/barrier layer.
15. The semiconductor die of claim 11 wherein said semiconductor die is enclosed in a semiconductor package.
16. The semiconductor die of claim 11 wherein said top conductive layer is formed over a passivation stack, said passivation stack being situated over said at least one interlayer dielectric layer.
17. The semiconductor die of claim 16 wherein said passivation stack comprises an upper passivation layer situated over a lower passivation layer, wherein said upper passivation layer comprises polyimide.
18. The semiconductor die of claim 11 wherein said top conductive layer is part of an inductor residing on said semiconductor die.
19. The semiconductor die of claim 11 wherein said top conductive layer is utilized to route power in said semiconductor die.
20. The semiconductor die of claim 11 wherein said top conductive layer is utilized to route ground in said semiconductor die.