Fabrication of high-density capacitors for mixed signal/RF circuits
View Patent ↗A method for fabricating a capacitor on a semiconductor substrate is disclosed. The method may include simultaneously forming at least one via and at least one upper capacitor plate opening in a first dielectric layer having an underlying cap dielectric layer deposited over a first material region having a first conductive material within a conductive region and forming a trench above the via. The underlying cap dielectric layer may be modified in a way that increases its dielectric constant as a result of simultaneously be heated by a heat source and impinged with and energy beam. The method may also include filling the via, trench, and upper capacitor plate opening with a second conductive material resulting in an integrated circuit structure and employing CMP to remove any excess second conductive material from the integrated circuit structure.
1. A method for fabricating a capacitor on a semiconductor substrate, the method comprising:
simultaneously forming at least one via and at least one upper capacitor plate opening in a first dielectric layer having an underlying cap dielectric layer deposited over a first material region having a first conductive material within a conductive region, whereby the at least one via exposes a via area of the cap dielectric layer and the at least one upper capacitor plate opening exposes an upper capacitor plate opening area of the can dielectric layer;
simultaneously heating the cap dielectric layer with a heat source and impinging the exposed via area and exposed upper capacitor plate opening area of the cap dielectric layer with an energy beam, whereby the cap dielectric layer is modified in the via area and the upper capacitor plate opening area such that the dielectric values of the via area and the upper capacitor plate opening area are higher than the dielectric value of the remaining portions of the dielectric layer;
forming a trench above the via; and
filling the via, trench, and upper capacitor plate opening with a second conductive material resulting in an integrated circuit structure.
2. The method of claim 1 , wherein the step of simultaneously forming a via and an upper capacitor plate opening in a first dielectric layer further includes:
depositing the first dielectric layer over the cap dielectric layer;
applying a first photo-resist over the fist dielectric layer to form a pattern for the via and the upper capacitor plate opening;
etching the via and the upper capacitor plate opening in the first dielectric layer; and
stripping the first photo-resist from the first dielectric layer.
3. The method of claim 2 , wherein the step of forming a trench above the via includes:
applying a second photo-resist over the first dielectric layer having a via and upper capacitor plate opening contained therein to form a trench pattern above the via;
etching the trench in the first dielectric layer and removing the cap dielectric layer from a bottom of the via resulting in an etched structure; and
stripping the second photo-resist from the etched structure.
4. The method of claim 1 , wherein the cap dielectric layer functions as an insulator of the capacitor.
5. The method of claim 1 , wherein the first conductive material and second conductive material comprise at least one of a metal, a polysilicon, or a silicon substrate.
6. The method of claim 5 , wherein the first conductive material and second conductive material each include a metal to form a metal-insulator-metal (“MIM”) capacitor.
7. The method of claim 1 , wherein the at least one via has a via height and the trench has a trench height, and the upper capacitor plate opening has upper capacitor plate opening height that is approximately equal to a combined height of the via height and the trench height.
8. The method of claim 1 , wherein the cap dielectric layer is heated to a temperature equal to or less than 450C.
9. The method of claim 8 , wherein the cap dielectric layer is heated to a temperature equal to or less than 400C.
10. The method of claim 1 comprising employing CMP to remove any excess second conductive material from the integrated circuit structure.
11. The method of claim 5 , wherein the first conductive material and second conductive material each include a polysilicon to form a polysilicon-insulator-polysilicon (“PIP”) capacitor.
12. The method of claim 5 , wherein the first conductive material includes a metal and the second conductive material includes a silicone substrate to form a metal-insulator- silicon (“MIS”) capacitor.
13. The method of claim 5 , wherein the first conductive material includes a polysilicon and the second conductive material includes a silicone substrate to form a polysilicon-insulator-silicon (“PIS”) capacitor.