Method for fabricating a high density composite MIM capacitor with reduced voltage dependence in semiconductor dies
View Patent ↗According to a disclosed embodiment, a composite MIM capacitor comprises a lower electrode of a lower MIM capacitor situated in a lower interconnect metal layer of a semiconductor die. The composite MIM capacitor further comprises an upper electrode of the lower MIM capacitor situated within a lower interlayer dielectric, where the lower interlayer dielectric separates the lower interconnect metal layer from an upper interconnect metal layer. A lower electrode of the upper MIM capacitor is situated in the upper interconnect metal layer. An upper electrode of the upper MIM capacitor is situated within the upper interlayer dielectric which is, in turn, situated over the upper interconnect metal layer. The upper electrode of the lower MIM capacitor is connected to the lower electrode of the upper MIM capacitor while the lower electrode of the lower MIM capacitor is connected to the upper electrode of the upper MIM capacitor.
1. A method for fabricating a composite capacitor in a semiconductor die, said method comprising steps of:
depositing a lower interconnect metal layer;
forming an upper electrode of a lower capacitor over said lower interconnect metal layer;
patterning said lower interconnect metal layer to form a lower electrode of said lower capacitor;
depositing an interlayer dielectric layer over said upper electrode and said lower electrode of said lower capacitor;
depositing an upper interconnect metal layer over said interlayer dielectric layer;
forming an upper electrode of an upper capacitor over said upper interconnect metal layer;
patterning said upper interconnect metal layer to form a lower electrode of said upper capacitor;
wherein said lower electrode of said lower capacitor is electrically connected to said upper electrode of said upper capacitor so as to couple said lower capacitor and said upper capacitor in a parallel configuration.
2. The method of claim 1 further comprising a step of connecting said upper electrode of said lower capacitor to said lower electrode of said upper capacitor by at least one via.
3. The method of claim 1 further comprising a step of connecting said lower electrode of said lower capacitor to said upper electrode of said upper capacitor by at least one via.
4. The method of claim 1 further comprising a step of forming a high-k dielectric between said lower and upper electrodes of said lower capacitor.
5. The method of claim 4 wherein said high-k dielectric is selected from the group consisting of silicon oxide, silicon nitride, tantalum pentoxide, aluminum oxide, hafnium oxide, zirconium oxide, zirconium aluminum silicate, hafnium silicate, and hafnium aluminum silicate.
6. The method of claim 1 further comprising a step of forming a high-k dielectric between said lower and upper electrodes of said upper capacitor.
7. The method of claim 6 wherein said high-k dielectric is selected from the group consisting of silicon oxide, silicon nitride, tantalum pentoxide, aluminum oxide, hafnium oxide, zirconium oxide, zirconium aluminum silicate, hafnium silicate, and hafnium aluminum silicate.
8. The method of claim 1 wherein said upper electrode of said lower capacitor and said upper electrode of said upper capacitor comprise metal selected from the group consisting of titanium nitride and tantalum nitride.
9. The method of claim 1 wherein said upper electrode of said lower capacitor and said upper electrode of said upper capacitor are fabricated utilizing a common mask.