Method and arrangement for instruction word generation in the controlling of functional units in a processor
View Patent ↗The invention relates to a method and an arrangement for instruction word generation in the controlling of functional units in a processor, the instruction words comprising a plurality of instruction word parts. In this case, in a program sequence, under the control of a program word, an instruction word is taken from a row—determined by a reading row number—of an instruction word memory that can be written to row by row, the said instruction word is altered by means of substitution of an instruction word part by the information part of the respective program word and is written back to a row of the instruction word memory, the said row being determined by a writing row number. Afterwards, an instruction word—which is generated in this way and is to be executed in accordance with the program—for controlling the functional units is output to the processor. According to the invention, a reduction in the processing width and an increase in the operating speed is achieved by the writing and reading row numbers being generated by corresponding registers and/or the largest possible number of instruction words that are to be executed being successively compiled in the instruction word memory and processed, so that they are combined in blocks. This makes it possible to reduce the processing width during the program word processing in the part which carries control information.
1. A method for generation of instruction words in a digital processor having an instruction word memory wherein instruction words are arranged in rows, each instruction word having a plurality of instruction word parts, each driving a functional unit of said processor, comprising:
deriving primary instruction words from a program code;
combining said primary instruction words into a sequence of associated program words;
reading an instruction word from a row of said instruction word memory determined by a reading row number;
modifying said read instruction word by substituting an instruction word part with an information part of an associated program word;
writing said modified instruction word part to a row of said instruction word memory determined by a writing row number; and
outputting a completed instruction word to drive said functional units of said processor,
wherein said reading row number and said writing row number are provided by respective reading row and writing row registers, and wherein a number of sequential reading row and writing row numbers are determined by contents of a block length register.
2. A method as specified in claim 1 , further providing re-setting contents of said reading row register, said writing row register and said block length register by providing a program word having a set bit, which in an active state designates information parts of said program word as containing data for re-setting said registers.
3. A method as specified in claim 2 wherein said active state of said set bit causes said information parts of said program word to be stored in said registers.
4. A method as specified in claim 1 wherein said instruction register further includes a first instruction word page and a second instruction word page having the same row numbers, wherein there is provided a page register whose contents designate one of said pages as active.
5. A method according to claim 1 wherein if an instruction word is not called for during execution of a step of said instruction word generation, an additional instruction word is formed by a prefetch unit calling a subsequent sequence of associated program words.
6. A method for the generation of instruction words in a digital processor having an instruction word memory wherein instruction words are arranged in rows, each instruction word having a plurality of instruction word parts, each driving a functional unit of said processor, comprising:
deriving primary instruction words from a program code;
assembling said primary instruction words into a sequence of associated program words;
reading an instruction word from a row and page of said instruction word memory determined by a reading row number and a page number stored in a page register;
modifying said instruction word by substituting an instruction word part with an information part of an associated program word;
writing said modified instruction word to a row and page of said instruction word memory determined by a writing row number and a page number stored in said page register; and
outputting a completed instruction word to control said functional units of said processor.
7. A method according to claim 6 wherein an interrupt signal during execution of a first task by said processor, wherein said instruction words are stored in a first page of said instruction word memory, causes said processor to generate instruction words using a second page of said instruction word memory for a second interrupt task, and on completion of said second interrupt task to return to said instruction words stored on said first page of said instruction word memory.
8. A method according to claim 6 wherein if an instruction word is not called during execution of a step of said instruction word generation, an additional instruction word is formed by a prefetch unit calling a subsequent sequence of associated program words.