Arithmetic unit and receiver unit
View Patent ↗There are provided an arithmetic unit and a receiver unit which execute an arithmetic operation at a high speed and allow reduction of the size thereof. An input section inputs data of the data group. First to n-th (n>1) storage sections have a capacity capable of storing at least part or all of the data group. A readout section selects one of the first to n-th storage sections and reads out therefrom a data group already stored therein. An arithmetic section performs a predetermined arithmetic operation between the data group read out by the readout section and the data group newly inputted by the input section. A writing section writes a result of the predetermined arithmetic operation by the arithmetic section in a predetermined one of the storage sections, which is not selected by the reading section as the one from which the data group already stored therein is to be read out.
1. An arithmetic unit that receives a data group formed of a plurality of data, and performs a predetermined arithmetic processing operation between the data group and another data group inputted earlier,
the arithmetic unit comprising:
input portion for inputting data of the data group;
first to n-th (n>1) storage portion each having a capacity capable of storing at least part or all of the data group;
readout portion for selecting one of the first to n-th storage portion and reading out therefrom a data group already stored therein;
arithmetic portion for performing a predetermined arithmetic operation between the data group read out by the readout portion and the data group newly inputted by the input portion;
writing portion for writing a result of the predetermined arithmetic operation by the arithmetic portion in one of the first to n-th storage portion, wherein the storage portion in which the result is to be written is not selected by the readout portion as the one from which the data group already stored therein is to be read out; and
output portion for outputting date of the result of the predetermined arithmetic operation stored in one of the first to n-th storage portion.
2. The arithmetic unit according to claim 1 , wherein the first to n-th storage portion are formed by a memory array, and wherein the memory array is used in a bank switching manner so as to be used as the first to n-th storage portion.
3. The arithmetic unit according to claim 2 , wherein the memory array is formed by single port memories.
4. The arithmetic unit according to claim 1 , further comprising address-generating portion for generating addresses which are accessed by the readout portion and the writing portion, and
wherein by using a predetermined bit of each address generated by the address-generating portion, ones of the first to n-th storage portion which are to be accessed by the readout portion and the writing portion are specified.
5. The arithmetic unit according to claim 1 , wherein the readout portion reads out data prior to writing by the writing portion.
6. The arithmetic unit according to claim 1 , wherein the arithmetic portion executes addition to thereby perform integrating operation in units of data groups.
7. The arithmetic unit according to claim 1 , comprising:
operation start-instructing portion for instructing the predetermined arithmetic processing operation to be started, and
initializing portion for setting all data of a first data group supplied from the readout portion to an initial value of “0” when the operation start-instructing portion instructs the predetermined arithmetic processing operation to be started.
8. The arithmetic unit according to claim 1 , further comprising:
counting portion for counting a number of times of the arithmetic processing operations performed in units of blocks, and
stoppage portion for stopping the predetermined arithmetic processing operation when a value counted by the counting portion reaches a predetermined set value.
9. The arithmetic unit according to claim 1 , further comprising set value-changing portion for changing a predetermined set value.
10. A receiver unit that receives a data group formed of a plurality of data, and performs a predetermined arithmetic processing operation between the data group and another data group inputted earlier,
the receiver unit comprising:
input portion for inputting data of the data group;
first to n-th (n>1) storage portion each having a capacity capable of storing at least part or all of the data group;
readout portion for selecting one of the first to n-th storage portion and reading out therefrom a data group already stored therein;
arithmetic portion for performing a predetermined arithmetic operation between the data group read out by the readout portion and the data group newly inputted by the input portion;
writing portion for writing a result of the predetermined arithmetic operation by the arithmetic portion in one of the first to n-th storage portion, wherein the storage portion in which the result is to be written is not selected by the readout portion as the one from which the data group already stored therein is to be read out; and
output portion for outputting date of the result of the predetermined arithmetic operation stored in one of the first to n-th storage portion.
11. The receiver unit according to claim 10 , wherein the first to n-th storage portion are formed by a memory array, and wherein the memory array is used in a bank switching manner so as to be used as the first to n-th storage portion.
12. The receiver unit according to claim 11 , wherein the memory array is formed by single port memories.
13. The receiver unit according to claim 10 , further comprising address-generating portion for generating addresses which are accessed by the readout portion and the writing portion, and
wherein by using a predetermined bit of each address generated by the address-generating portion, ones of the first to n-th storage portion which are to be accessed by the readout portion and the writing portion are specified.
14. The receiver unit according to claim 10 , wherein the readout portion reads out data prior to writing by the writing portion.
15. The receiver unit according to claim 10 , wherein the arithmetic portion executes addition to thereby perform integrating operation in units of data groups.
16. The receiver unit according to claim 10 , comprising:
operation start-instructing portion for instructing the predetermined arithmetic processing operation to be started, and
initializing portion for setting all data of a first data group supplied from the readout portion to an initial value of “0” when the operation start-instructing portion instructs the predetermined arithmetic processing operation to be started.
17. The receiver unit according to claim 10 , further comprising:
counting portion for counting a number of times of the arithmetic processing operations performed in units of blocks, and
stoppage portion for stopping the predetermined arithmetic processing operation when a value counted by the counting portion reaches a predetermined set value.
18. The receiver unit according to claim 10 , further comprising set value-changing portion for changing a predetermined set value.