Deep trench isolation of embedded DRAM for improved latch-up immunity
View Patent ↗A protective structure for blocking the propagation of defects generated in a semiconductor device is disclosed. In an exemplary embodiment, the structure includes a deep trench isolation formed between a memory storage region of the semiconductor device and a logic circuit region of the semiconductor device, the deep trench isolation being filled with an insulative material. The deep trench isolation thereby prevents the propagation of crystal defects generated in the logic circuit region from propagating into the memory storage region.
1. A protective structure for blocking the propagation of defects generated in a semiconductor device, the structure comprising:
a plurality of deep trench isolations formed between a memory storage region of the semiconductor device and a logic circuit region of the semiconductor device, said plurality of deep trench isolations being filled with an insulative material;
said plurality of deep trench isolations further comprising an inner perimeter and an outer perimeter, wherein individual deep trench isolations included in said outer perimeter are disposed adjacent to gaps in between individual deep trench isolations included in said inner perimeter; and
wherein said plurality of deep trench isolations prevent the propagation of crystal defects generated in said logic circuit region from propagating into said memory storage region.
2. The structure of claim 1 , wherein each of said plurality of deep trench isolations are formed beneath a corresponding shallow trench isolation, said shallow trench isolation for electrically isolating devices contained in said memory storage region from devices contained in said logic circuit region.
3. The structure of claim 1 , wherein said plurality of deep trench isolations surround said memory storage region.
4. The structure of claim 1 , wherein said memory storage region comprises a DRAM array region.
5. The structure of claim 1 , wherein said memory storage region comprises a DRAM array region.
6. The structure of claim 5 , wherein said logic circuit region further includes:
a plurality of CMOS devices; and
a high dose impurity layer implanted within a substrate of said logic circuit region, said high dose impurity layer used to inhibit parasitic bipolar transistor action between said plurality of CMOS devices.
7. An embedded DRAM (eDRAM) device, comprising:
a logic circuit region;
a memory storage region embedded adjacent said logic circuit region;
a shallow trench isolation for electrically insulating devices included within said memory storage region from devices included within said logic circuit region;
a plurality of deep trench isolations, formed underneath said shallow trench isolation, said plurality of deep trench isolations for preventing the propagation of crystal defects generated in said logic circuit region from propagating into said memory storage region; and
said plurality of deep trench isolations further comprising an inner perimeter and an outer perimeter, wherein individual deep trench isolations included in said outer perimeter are disposed adjacent to gaps in between individual deep trench isolations included in said inner perimeter.
8. The eDRAM device of claim 7 , wherein said shallow trench isolation surrounds said memory storage region.
9. The eDRAM device of claim 8 , wherein said plurality of deep trench isolations surround said memory storage region.
10. The eDRAM device of claim 8 , wherein said memory storage region includes a plurality of deep trench storage capacitors.
11. The eDRAM device of claim 10 , wherein said logic circuit region further includes:
a plurality of CMOS devices; and
a high dose impurity layer implanted within a substrate of said logic circuit region, said high dose impurity layer used to inhibit parasitic bipolar transistor action between said plurality of CMOS devices.