Patent Assignment
Reel/Frame 054528/0023
Assignment of Assignor's Interest
Recorded: 2020-11-26
Pages: 9
Assignor
INTERNATIONAL BUSINESS MACHINES CORPORATION
Executed: 2020-09-29
Assignee
ELPIS TECHNOLOGIES INC.
1891 ROBERTSON ROAD, SUITE 100, OTTAWA, K2H 5B7, CANADA
Covered Properties
(107)
Process of Enclosing via for Improved Reliability in Dual Damascene Interconnects
Patent:
6,383,920 →
Application:
09/757,894 →
Encapsulant Composition and Electronic Package Utilizing Same
C Implants for Improved Sige Bipolar Yield
Bipolar Transistor with Raised Extrinsic Base Fabricated in an Integrated Bicmos Circuit
Vertical Dual Gate Field Effect Transistor
Deep Trench Isolation of Embedded Dram for Improved Latch-Up Immunity
Semiconductor Chip Using Both Polysilicon and Metal Gate Devices
Damascene Gate Multi-Mesa Mosfet
Bipolar Transistor with Raised Extrinsic Base Fabricated in an Integrated Bicmos Circuit
C Implants for Improved Sige Bipolar Yield
Method of Base Formation in a Bicmos Process
High Ft and Fmax Bipolar Transistor and Method of Making Same
A Method of Base Formation in a Bicmos Process
Patent:
6,911,681 →
Application:
10/709,113 →
Method of Collector Formation in Bicmos Technology
Patent:
7,002,190 →
Application:
10/711,479 →
C Implants for Improved Sige Bipolar Yield
Embedded Stressed Nitride Liners for Cmos Performance Improvement
Vertical Dual Gate Field Effect Transistor
Structure and Method to Generate Local Mechanical Gate Stress for Mosfet Channel Mobility Modification
Deep Trench Isolation of Embedded Dram for Improved Latch-Up Immunity
Damascene Gate Multi-Mesa Mosfet
Low-Cost High-Performance Planar Back-Gate Cmos
Mosfet with High Angle Sidewall Gate and Contacts for Reduced Miller Capacitance
Rotational Shear Stress for Charge Carrier Mobility Modification
Method of Collector Formation in Bicmos Technology
Structure and Method for Making High Density Mosfet Circuits with Different Height Contact Lines
Semiconductor Device Structure Having Enhanced Performance Fet Device
High Ft and Fmax Bipolar Transistor and Method of Making Same
Dual Stress Liner
Structure and Method to Form Multilayer Embedded Stressors
Sub-Lithographic Nano Interconnect Structures, and Method for Forming Same
Sub-Lithographic Gate Length Transistor Using Self-Assembling Polymers
Dual Liner Capping Layer Interconnect Structure and Method
Structure and Method to Generate Local Mechanical Gate Stress for Mosfet Channel Mobility Modification
Method of Forming Stressed Soi Fet Having Doped Glass Box Layer Using Sacrifical Stressed Layer
Sub-Lithographic Interconnect Patterning Using Self-Assembling Polymers
Stressed Soi Fet Having Tensile and Compressive Device Regions
Stressed Dielectric Devices and Methods of Fabricating Same
Encapsulant Composition and Electronic Package Utilizing Same
Electronic Package with Epoxy or Cyanate Ester Resin Encapsulant
A Planar Field Effect Transistor Structure Having an Angled Crystallographic Etch-Defined Source/Drain Recess and a Method of Forming the Transistor Structure
Structure and Method for Making High Density Mosfet Circuits with Different Height Contact Lines
Embedded Stressed Nitride Liners for Cmos Performance Improvement
Low-Cost High-Performance Planar Back-Gate Cmos
Rotational Shear Stress for Charge Carrier Mobility Modification
Embedded Stressed Nitride Liners for Cmos Performance Improvement
Method for Dual Stress Liner
Sub-Lithographic Gate Length Transistor Using Self-Assembling Polymers
Encapsulant of Epoxy or Cyanate Ester Resin, Reactive Flexibilizer and Thermoplastic
Dual Liner Capping Layer Interconnect Structure
Dual Liner Capping Layer Interconnect Structure
Self-Aligned Contact
Stressed Dielectric Devices and Methods of Fabricating Same
Structure and Method to Form Multilayer Embedded Stressors
Semiconductor Device Structure Having Enhanced Performance Fet Device
A Planar Field Effect Transistor Structure Having an Angled Crystallographic Etch-Defined Source/Drain Recess and a Method of Forming the Transistor Structure
Contact Structures for Semiconductor Transistors
Tapered Nanowire Structure with Reduced Off Current
Double Patterning Method
Method of Forming a Planar Field Effect Transistor Structure with Recesses for Epitaxially Deposited Source/Drain Regions
Replacement Metal Gate Finfet
Replacement Metal Gate Finfet
Dummy Gate Interconnect for Semiconductor Device
Field Effect Transistor Including a Regrown Contoured Channel
Method of Epitaxially Forming Contact Structures for Semiconductor Transistors
Thin-Film Ambipolar Logic
Tapered Nanowire Structure with Reduced Off Current
Double Patterning Method
Replacement Metal Gate Finfet
Replacement Metal Gate Finfet
Replacement Metal Gate Finfet
Electronic Package with Heat Transfer Element(S)
Thin-Film Ambipolar Logic
Manufacturing Electronic Package with Heat Transfer Element(S)
Channel Protection During Fin Fabrication
Patent:
9,496,371 →
Application:
14/877,051 →
Fabrication of Semiconductor Junctions
Voidless Contact Metal Structures
Patent:
9,449,921 →
Application:
14/969,822 →
Soi Lateral Bipolar for Integrated-Injection Logic Sram
Patent:
9,472,556 →
Application:
14/997,176 →
Semiconductor Device Strain Relaxation Buffer Layer
Patent:
9,698,266 →
Application:
15/064,670 →
Air-Core Inductors and Transformers
Voidless Contact Metal Structures
Voidless Contact Metal Structures
Self-Aligned Trench Metal-Alloying for Iii-V Nfets
Conformal Capacitor Structure Formed by a Single Process
Independent Gate Finfet with Backside Gate Contact
Semiconductor Device Strain Relaxation Buffer Layer
Heat Pipe and Vapor Chamber Heat Dissipation
Patent:
10,045,464 →
Application:
15/475,529 →
Heat Pipe and Vapor Chamber Heat Dissipation
Patent:
9,980,410 →
Application:
15/718,415 →
Wafer Scale Testing and Initialization of Small Die Chips
Wafer Scale Testing and Initialization of Small Die Chips
Substrate with a Fin Region Comprising a Stepped Height Structure
Beol Embedded High Density Vertical Resistor Structure
Techniques for Forming Different Gate Length Vertical Transistors with Dual Gate Oxide
Independent Gate Finfet with Backside Gate Contact
Air Gap Spacer with Controlled Air Gap Height
Techniques for Vertical FET Gate Length Control
Close Proximity and Lateral Resistance Reduction for Bottom Source/Drain Epitaxy in Vertical Transistor Devices
Self-Limiting Fin Spike Removal
Enabling Low Resistance Gates and Contacts Integrated with Bilayer Dielectrics
Patent:
10,204,828 →
Application:
15/893,232 →
Electronic Devices Having Spiral Conductive Structures
Structure and Method for Improving Access Resistance in U-Channel Etsoi
Transparent Electronics for Invisible Smart Dust Applications
Patent:
10,396,061 →
Application:
15/928,873 →
Fabrication of Semiconductor Junctions
Heat Pipe and Vapor Chamber Heat Dissipation
Conformal Capacitor Structure Formed by a Single Process
Electronic Devices Having Spiral Conductive Structures
Self-Limiting Fin Spike Removal
Beol Embedded High Density Vertical Resistor Structure
Related Assignments
(15)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Jan 10, 2001
From: WANG, PING-CHUAN; FILIPPI, RONALD G.; EDWARDS, ROBERT D.; KIEWRA, EDWARD W.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 011494/0785 →
Assignment of Assignor's Interest
Feb 7, 2001
From: PAPATHOMAS, KONSTANTINOS I.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 011547/0339 →
Assignment of Assignor's Interest
Jun 11, 2001
From: COOLBAUGH, DOUGLAS D.; SCHONENBERG, KATHRYN T.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 011915/0423 →
Assignment of Assignor's Interest
Aug 31, 2001
From: FURUKAWA, TOSHIHARU; HAKEY, MARK C.; HOLMES, STEVER J.; HORAK, DAVID V.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 012163/0911 →
Assignment of Assignor's Interest
Oct 11, 2001
From: HUANG, FENG-YI; TICKNOR, ADAM D.; AHLGREN, DAVID C.; FREEMAN, GREGORY G.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 012264/0106 →
Assignment of Assignor's Interest
Feb 22, 2002
From: CHEN, TZE-CHIANG; HAN, LIANG-KAI
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 012663/0205 →
Assignment of Assignor's Interest
Aug 6, 2002
From: CLEVENGER, LAWRENCE A.; HSU, LOUIS L.; WONG, KWONG HON
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 013187/0124 →
Assignment of Assignor's Interest
Oct 1, 2002
From: FURUKAWA, TOSHIHARU; MANDELMAN, JACK A.; PARK, BYEONGJU
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 013359/0767 →
Assignment of Assignor's Interest
Jun 24, 2003
From: JOSEPH, ALVIN JOSE; LIU, QIZHI
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 013753/0374 →
Assignment of Assignor's Interest
Apr 14, 2004
From: GEISS, PETER J.; JOSEPH, ALVIN J.; LIU, QIZHI; ORNER, BRADLEY A.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 014502/0215 →
Assignment of Assignor's Interest
Jun 10, 2004
From: CHIDAMBARRAO, DURESETI; DOKUMACI, OMER H.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 014716/0098 →
Assignment of Assignor's Interest
Sep 21, 2004
From: GEISS, PETER J.; GRAY, PETER B.; JOSEPH, ALVIN J.; LIU, QIZHI
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 015154/0174 →
Assignment of Assignor's Interest
Dec 15, 2004
From: CABRAL, JR., CYRIL; DORIS, BRUCE B.; KANARSKY, THOMAS S.; LIU, XIAO H.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 015456/0209 →
Assignment of Assignor's Interest
Oct 16, 2006
From: GEISS, PETER J.; JOSEPH, ALVIN J.; LIU, QIZHI; ORNER, BRADLEY A.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 018391/0639 →
Corrective Assignment to Correct the Spelling of 3RD and 7TH Assignor's Names Previously Recorded on Reel 012163 Frame 0911. Assignor(S) Hereby Confirms the Assignment.
May 19, 2020
From: FURUKAWA, TOSHIHARU; HAKEY, MARK C.; HOLMES, STEVEN J.; HORAK, DAVID V.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 052697/0960 →