IP Library Granted Patent US 7,339,230
Granted Patent B2
US 7,339,230 · App. 11/306,707 · Granted Mar 4, 2008

Structure and method for making high density mosfet circuits with different height contact lines

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Quick Facts
Patent No.
US 7,339,230
App. No.
11/306,707
Granted
Mar 4, 2008
Kind
B2
Abstract

Embodiments herein present a structure, method, etc. for making high density MOSFET circuits with different height contact lines. The MOSFET circuits include a contact line, a first gate layer situated proximate the contact line, and at least one subsequent gate layer situated over the first gate layer. The contact line includes a height that is less than a combined height of the first gate layer and the subsequent gate layer(s). The MOSFET circuits further include gate spacers situated proximate the gate layers and a single contact line spacer situated proximate the contact line. The gate spacers are taller and thicker than the contact line spacer.

Claims (22)

1. A MOSFET circuit, comprising:

a contact line;

a first gate layer situated proximate said contact line, wherein said contact line comprises a height that is less than a height of said first gate layer, and

a polysilicon germanium gate layer situated above said first gate layer and below at least one subsequent gate layer.

2. The MOSFET circuit according to claim 1 , all the limitations of which are incorporated herein by reference, further comprising:

gate spacers situated proximate said first gate layer; and

a single contact line spacer situated proximate said contact line,

wherein said contact line spacer comprises a height that is less than a height of said gate spacers.

3. The MOSFET circuit according to claim 1 , all the limitations of which are incorporated herein by reference, further comprising:

gate spacers situated proximate said first gate layer; and

a single contact line spacer situated proximate said contact line,

wherein said contact line spacer comprises a thickness that is less than a thickness of said gate spacers.

4. A MOSFET circuit, comprising:

a contact line;

a first gate layer situated proximate said contact line;

at least one second gate layer situated over said first gate layer;

gate spacers situated proximate said first gate layer and said second gate layer;

less than two contact line spacers situated proximate said contact line; and

a polysilicon germanium gate layer situated above said first gate layer and below at least one subsequent gate layer.

5. The MOSFET circuit according to claim 4 , all the limitations of which are incorporated herein by reference, wherein said contact line comprises a height that is less than a combined height of said first gate layer and said second gate layer.

6. The MOSFET circuit according to claim 4 , all the limitations of which are incorporated herein by reference, wherein said less than two contact line spacers comprises a height that is less than a height of said gate spacers.

7. The MOSFET circuit according to claim 4 , all the limitations of which are incorporated herein by reference, wherein said less than two contact line spacers comprises a thickness that is less than a thickness of said gate spacers.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 26, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: ELPIS TECHNOLOGIES INC.
Reel/Frame 054528/0023 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 9, 2006
From: ZHU, HUILONG
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 016985/0810 →