Low-cost high-performance planar back-gate CMOS
View Patent ↗A method of fabricating a high-performance planar back-gate CMOS structure having superior short-channel characteristics and reduced capacitance using processing steps that are not too lengthy or costly is provided. Also provided is a high-performance planar back-gate CMOS structure that is formed utilizing the method of the present invention. The method includes forming an opening in an upper surface of a substrate. Thereafter, a dopant region is formed in the substrate through the opening. In accordance with the inventive method, the dopant region defines a back-gate conductor of the inventive structure. Next, a front gate conductor having at least a portion thereof is formed within the opening.
1. A method of forming a planar back-gate CMOS structure comprising:
providing a semiconductor-on-insulator (SOI) substrate including a bottom semiconductor layer, a buried insulating layer, and a top semiconductor layer;
forming an opening in an upper surface of said top semiconductor layer;
forming a dopant region in said bottom semiconductor layer by implanting dopants through said opening, said dopant region defining a back-gate conductor; and
forming a front gate conductor having at least a portion thereof within said opening.
2. The method of claim 1 further comprising forming source/drain regions in said upper surface of said top semiconductor layer, said source/drain regions are located adjacent to opposite sides of said front gate conductor.
3. The method of claim 1 , wherein a region of said top semiconductor layer within said opening is thinned to a thickness from about 5 to about 25 nm by oxidation and etching.
4. The method of claim 1 , further comprising forming at least one trench isolation region and a trench contact within said SOI substrate prior to forming said opening.
5. The method of claim 1 , wherein said opening in said upper surface of said top semiconductor layer is formed by
(i) providing a material stack on said SOI substrate,
(ii) forming a patterned mask on said material stack, said patterned mask having another opening that exposes said material stack, and
(iii) etching exposed portions of said material stack to expose a portion of said top semiconductor layer, wherein said etching removes a surface portion of said top semiconductor layer.
6. The method of claim 5 , further comprising a thinning step, wherein said thinning step thins said exposed portion of said top semiconductor layer to a thickness within a range from about 5 to about 25 nm.
7. The method of claim 1 , wherein said bottom semiconductor layer is doped with dopant of a first conductivity type, wherein said dopant region is formed by ion implanting a second conductivity type dopant within said bottom semiconductor layer through said opening, wherein said dopant region having a dopant concentration from about 10 19 to about 10 21 atoms/cm 3 , and wherein said second conductivity type is different from said first conductivity type.
8. The method of claim 1 , further comprising forming a second dopant region about said back-gate conductor, wherein said bottom semiconductor layer is doped with dopant of a first conductivity type, wherein said second dopant region has a dopant concentration that is less than that of said back-gate conductor, and wherein said second conductivity type is different from said first conductivity type.
9. The method of claim 2 , further comprising forming a silicide atop said source/drain regions.
10. The method of claim 1 , further comprising forming an interconnect structure on said top semiconductor layer, said interconnect structure including an interlevel dielectric having conductively filled vias and lines located therein.
11. The method of claim 9 , further comprising forming another silicide atop said front gate conductor.