IP Library Granted Patent US 9,153,447
Granted Patent B2
US 9,153,447 · App. 13/672,899 · Granted Oct 6, 2015

Replacement metal gate FinFET

Inventors: Hemanth Jagannathan (Guilderland, NY); Sanjay C. Mehta (Niskayuna, NY); Junli Wang (Singerlands, NY); Chun-Chen Yeh (Clifton Park, NY); Stefan Schmitz (Century Drive, NY)
Assignee: International Business Machines Corporation
H01L21/28132H01L29/66545H01L29/66795H01L29/78H01L29/785
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Quick Facts
Patent No.
US 9,153,447
App. No.
13/672,899
Granted
Oct 6, 2015
Kind
B2
Abstract

A field effect transistor device includes a fin including a semiconductor material arranged on an insulator layer, the fin including a channel region, a hardmask layer arranged partially over the channel region of the fin, a gate stack arranged over the hardmask layer and over the channel region of the fin, a metallic alloy layer arranged on a first portion of the hardmask layer, the metallic alloy layer arranged adjacent to the gate stack, and a first spacer arranged adjacent to the gate stack and over the metallic alloy layer.

Claims (10)

1. A field effect transistor (FET) device, comprising:

a fin including a semiconductor material arranged on an insulator layer, the fin including a channel region;

a hardmask layer disposed on the top surface of the fin, over the channel region,

a metallic alloy layer having first and second portions disposed on opposing ends of the hardmask layer, and over the channel region;

a gate stack formed on the hardmask layer and over the channel region, between the first and second portions of the metallic alloy layer, the gate stack including a dielectric layer; and

sidewall spacers adjacent sidewalls of the gate stack and over the channel region, wherein bottom surfaces of the sidewall spacers are formed on the first and second portions of the metallic alloy layer.

2. The FET device of claim 1 , wherein the gate stack comprises one or more of the dielectric layer, a work function metal layer, and a metallic gate material.

3. The FET device of claim 1 , wherein the metallic alloy layer includes a titanium nitride (TiN) material.

4. The FET device of claim 1 , wherein the hardmask layer includes an oxide material.

5. The FET device of claim 1 , wherein the sidewall spacers comprise one of an oxide material and a nitride material.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 26, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: ELPIS TECHNOLOGIES INC.
Reel/Frame 054528/0023 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2012
From: JAGANNATHAN, HEMANTH; MEHTA, SANJAY C.; WANG, JUNLI; YEH, CHUN-CHEN; SCHMITZ, STEFAN
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 029269/0880 →
Continuity (2)
Continuation 13659202 · Oct 24, 2012
Related Publication 20140110785A1 · Apr 24, 2014