Method of base formation in a BiCMOS process
View Patent ↗Disclosed is a bipolar complementary metal oxide semiconductor (BiCMOS) or NPN/PNP device that has a collector, an intrinsic base above the collector, shallow trench isolation regions adjacent the collector, a raised extrinsic base above the intrinsic base, a T-shaped emitter above the extrinic base, spacers adjacent the emitter, and a silicide layer that is separated from the emitter by the spacers.
1. A bipolar device comprising:
a base;
an emitter above said base, wherein said emitter has a T-shape with a lower section and an upper section that is wider than said lower section;
spacers adjacent said lower section of said emitter and beneath said upper section of said emitter;
non-silicided material adjacent said spacers; and
a silicide layer adjacent said non-silicided material and beneath said upper section of said emitter, wherein said non-silicided material is positioned between said spacers and said silicide layer.
2. The device in claim 1 , wherein said spacers separate said emitter from said silicide.
3. The device of claim 1 , wherein said base comprises:
an intrinsic base; and
an extrinsic base above said intrinsic base.
4. The device in claim 1 , wherein said spacers comprise insulators.
5. The device in claim 1 , wherein said silicide comprises a salicide.
6. A bipolar device comprising:
a base;
an emitter above said base, wherein said emitter has a T-shape with a lower section and an upper section that is wider than said lower section;
spacers adjacent said lower section of said emitter and beneath said upper section of said emitter;
a silicide layer adjacent said spacers and beneath said upper section of said emitter; and
a dielectric structure over said base and beneath said spacers.
7. The device in claim 6 , wherein said base is wider than said dielectric structure.
8. A transistor device comprising:
a lower semiconductor structure having a first-type impurity;
a middle semiconductor region above said lower semiconductor structure, said middle semiconductor region having a second-type impurity complementary to said first-type impurity;
an upper semiconductor structure above said middle semiconductor region, wherein said emitter has a T-shape with a lower section and an upper section that is wider than said lower section;
spacers adjacent said lower section of said emitter beneath said upper section of said emitter; and
non-silicided material adjacent said spacers; and
a silicide layer adjacent said non-silicided material and beneath said upper section of said emitter, wherein said non-silicided material is positioned between said spacers and said silicide layer.
9. The device in claim 8 , wherein said spacers separate said emitter from said silicide.
10. The device in claim 8 , wherein said middle semiconductor region comprises:
an intrinsic middle semiconductor region; and
an extrinsic middle semiconductor region above said intrinsic middle semiconductor region.
11. The device in claim 8 , wherein said spacers comprise insulators.
12. The device in claim 8 , wherein said silicide comprises a salicide.
13. A transistor device comprising:
a lower semiconductor structure having a first-type impurity;
a middle semiconductor region above said lower semiconductor structure, said middle semiconductor region having a second-type impurity complementary to said first-type impurity;
an upper semiconductor structure above said middle semiconductor region, wherein said emitter has a T-shape with a lower section and an upper section that is wider than said lower section;
spacers adjacent said section of said emitter and beneath said upper section of said emitter;
a silicide layer adjacent said spacers and beneath said upper section of said emitter, and
a dielectric structure over said middle semiconductor region and beneath said spacers.
14. The device in claim 13 , wherein said middle semiconductor region is wider than said dielectric structure.