Thin-film ambipolar logic
View Patent ↗An ambipolar electronic device is disclosed. The device may include a field-effect transistor (FET), which may have a handle substrate layer, two contacts and an inorganic crystalline layer between the handle substrate layer and the contacts. The inorganic crystalline layer may have a doped channel region between the contacts. The FET may also have a dielectric layer between the contacts, attached to the inorganic crystalline layer, and a gate layer, attached to the dielectric layer. The FET may conduct current, in response to a first gate voltage applied to the gate layer, using electrons as a majority carrier, along the length of the channel region between the contacts. The FET may also conduct current, in response to a second gate voltage applied to the gate layer, using holes as a majority carrier, along the length of the channel region between the contacts.
1. An ambipolar electronic device comprising:
a first FET (field-effect transistor) having:
a handle substrate layer;
a first contact;
a second contact;
an inorganic crystalline layer formed between a top surface of the handle substrate layer and the first and second contacts and having a channel region with a length extending between the first contact and the second contact;
a dielectric layer attached, between the first contact and the second contact, to a top surface of the inorganic crystalline layer; and
a gate layer, attached to a top surface of the dielectric layer;
wherein the first FET is configured to:
conduct current, in response to a first gate voltage applied to the gate layer and using electrons as a majority carrier, along the length of the channel region between the first contact and the second contact; and
conduct current, in response to a second gate voltage applied to the gate layer and using holes as a majority carrier, along the length of the channel region between the first contact and the second contact.
2. The electronic device of claim 1 , further comprising a buried insulator layer formed between the top surface of the handle substrate layer and the inorganic crystalline layer.
3. The electronic device of claim 1 , further comprising a metallic layer attached to a bottom surface of the handle substrate layer.
4. The electronic device of claim 1 , wherein a thickness of the inorganic crystalline layer is between 5 nm and 500 nm.
5. The electronic device of claim 1 , wherein the inorganic crystalline layer is one member of a group consisting of: predominantly silicon, predominantly germanium and predominantly silicon germanium.
6. The electronic device of claim 1 , wherein the first contact and the second contact include a metal with a work function within a range of +/−25% of an intrinsic Fermi energy in the channel region.
7. The electronic device of claim 6 , wherein the first contact and the second contact include a metal with a work function between 4.2 electron volts (eV) and 4.8 eV.
8. The electronic device of claim 6 , wherein the metal includes chromium.
9. The electronic device of claim 1 , wherein the dielectric layer has a dielectric constant between 3.9 and 25.
10. The electronic device of claim 1 , further comprising a second FET configured to provide ambipolar functionality in response to a gate voltage.
11. The electronic device of claim 10 , further comprising electrical connections that configure the first FET and the second FET as an inverter.
12. An ambipolar electronic device comprising:
a first FET (field-effect transistor) having:
a buried insulator layer attached to a top surface of handle substrate layer;
a first contact;
a second contact;
an inorganic crystalline layer formed between a top surface of the buried insulator layer and the first and second contacts and having a channel region with a length extending between the first contact and the second contact;
an insulating layer attached, between the first contact and the second contact, to a top surface of the inorganic crystalline layer;
a metallic layer formed below a bottom surface of the buried insulator layer;
wherein the first FET is configured to:
conduct current, in response to a first gate voltage applied to the metallic layer and using electrons as a majority carrier, along the length of the channel region between the first contact and the second contact; and
conduct current, in response to a second gate voltage applied to the metallic layer and using holes as a majority carrier, along the length of the channel region between the first contact and the second contact.
13. The electronic device of claim 12 , wherein the metallic layer is attached to a bottom surface of the handle substrate layer.
14. The electronic device of claim 12 , wherein the metallic layer is formed between a bottom surface of the buried insulator layer and the handle substrate layer.
15. The electronic device of claim 14 , wherein the metallic layer is patterned to overlap the channel region between the first contact and the second contact.