Embedded stressed nitride liners for CMOS performance improvement
View Patent ↗The present invention provides a semiconducting device including a gate region positioned on a mesa portion of a substrate; and a nitride liner positioned on the gate region and recessed surfaces of the substrate adjacent to the gate region, the nitride liner providing a stress to a device channel underlying the gate region. The stress produced on the device channel is a longitudinal stress on the order of about 275 MPa to about 450 MPa.
1. A semiconducting device comprising:
a semiconductor substrate having a mesa portion and recessed surfaces, wherein said mesa portion contains a mesa top surface and mesa sidewalls located above and adjoined to said recessed surfaces, and wherein said mesa top surface is vertically offset from said recessed surfaces;
a singled gated transistor comprising a gate region including a gate dielectric and a gate electrode, wherein said gate dielectric abuts said mesa top surface and is disjoined from said recessed surfaces and said mesa sidewalls;
silicide regions abutting said mesa top surface, said mesa sidewalls, and said recessed surfaces, wherein a portion of said silicide region is located below said recessed surfaces and another portion of said silicide region is located above said mesa top surface;
source and drain regions located under and aligned to said recessed surfaces; and
a nitride liner abutting said silicide regions not abutting said mesa top surface, wherein said nitride liner provides a longitudinal stress to a device channel underlying said gate region in said mesa portion of said semiconductor substrate.
2. The structure of claim 1 wherein said nitride liner comprises Si 3 N 4 .
3. The structure of claim 1 wherein said nitride liner has a thickness ranging from about 40 nm to about 100 nm.
4. The structure of claim 1 wherein said stress is produced in a portion of said device channel positioned about 5 nm or less below said gate region.
5. The structure of claim 1 wherein said mesa top surface is vertically offset from said recessed surfaces by a depth ranging from about 10 nm to about 100 nm.
6. The structure of claim 1 wherein the substrate comprises Si, bulk Si, single crystal Si, polycrystalline Si, SiGe, amorphous Si, silicon-on-insulator (SOI), SiGe-on-insulator (SGOI), annealed poly Si, poly Si line structures, GaAs, InAs, or a combination thereof.
7. The structure of claim 1 wherein said stress on said device channel, is a longitudinal stress ranging from about 350 MPa to about 550 MPa.
8. The structure of claim 1 further comprising a silicide region abutting and located beneath said recessed surfaces.
9. The structure of claim 1 further comprising source and drain extension regions located under and aligned to said mesa portion and extending beneath said sidewall spacers.
10. The structure of claim 1 further comprising a protective layer comprising a material selected from the group consisting of an oxide and a nitride, and having a thickness from about 2 nm to about 5 nm, wherein said protective layer abuts said gate electrode and said sidewall spacers.