Method of base formation in a BiCMOS process
View Patent ↗Disclosed is a bipolar complementary metal oxide semiconductor (BiCMOS) or NPN/PNP device that has a collector, an intrinsic base above the collector, shallow trench isolation regions adjacent the collector, a raised extrinsic base above the intrinsic base, a T-shaped emitter above the extrinsic base, spacers adjacent the emitter, and a silicide layer that is separated from the emitter by the spacers.
1. A method of making a transistor, said method comprising:
forming an extrinsic base above an intrinsic base, wherein before forming said extrinsic base;
patterning an insulator over said center of said intrinsic base; and
epitaxially growing said extrinsic base over said insulator and said intrinsic base;
protecting a portion of said extrinsic base using a sacrificial mask that is positioned over a center of said extrinsic base;
siliciding exposed portions of said extrinsic base, wherein said siliciding process leaves a non-silicided portion over said center of said extrinsic base;
forming an emitter opening though a center of said non-silicided portion of said extrinsic base;
forming spacers in said emitter opening; and
forming an emitter in said emitter opening, wherein said spacers separate said emitter from silicided portions of said extrinsic base.
2. The method in claim 1 , wherein said process of epitaxially growing said extrinsic base grows polysilicon above said insulator and single crystal silicon above the exposed portions of said intrinsic base.
3. The method in claim 1 , wherein said spacers are formed on said insulator.
4. The method in claim 1 , wherein said siliciding process forms said silicided portions of said extrinsic base horizontally adjacent to said non-silicided portion.
5. The method in claim 1 , further comprising, before forming said emitter opening, forming an insulator layer above said extrinsic base, wherein said emitter opening is formed though said insulator layer.
6. A method of making a transistor, said method comprising:
forming a lower semiconductor structure having a first-type impurity;
forming a middle semiconductor region above said lower semiconductor structure, said middle semiconductor region having a second-type impurity complementary to said first-type impurity, wherein before forming said middle semiconductor region:
forming a silicon layer over said lower semiconductor structure;
patterning an insulator over said center of said silicon layer; and
epitaxially growing said middle semiconductor region over said insulator and said silicon layer;
protecting a portion of said middle semiconductor region using a sacrificial mask that is positioned over a center of said middle semiconductor region;
siliciding exposed portions of said middle semiconductor region, wherein said siliciding process leaves a non-silicided portion over said center of said middle semiconductor region;
forming an upper semiconductor structure opening though a center of said non-silicided portion of said middle semiconductor region;
forming spacers in said upper semiconductor structure opening; and
forming an upper semiconductor structure in said upper semiconductor structure opening, wherein said spacers separate said upper semiconductor structure from silicided portions of said middle semiconductor region.
7. The method in claim 6 , wherein said process of epitaxially growing said middle semiconductor region grows polysilicon above said insulator and single crystal silicon above the exposed portions of said silicon layer.
8. The method in claim 6 , wherein said spacers are formed on said insulator.
9. The method in claim 6 , wherein said siliciding process forms said silicided portions of said middle semiconductor region horizontally adjacent to said non-silicided portion.
10. The method in claim 6 , further comprising, before forming said upper semiconductor structure opening, forming an insulator layer above said middle semiconductor region, wherein said upper semiconductor structure opening is formed though said insulator layer.
11. A method of making a bipolar complementary metal oxide semiconductor (BiCMOS) device, said method comprising:
forming a collector;
forming shallow trench isolation regions adjacent said collector;
forming an intrinsic base above said collector;
forming a raised extrinsic base above said intrinsic base, wherein before forming said extrinsic base:
patterning an insulator over said center of said intrinsic base; and
epitaxially growing said extrinsic base over said insulator and said intrinsic base;
protecting a portion of said extrinsic base using a sacrificial mask that is positioned over a center of said extrinsic base;
siliciding exposed portions of said extrinsic base, wherein said siliciding process leaves a non-silicided portion over said center of said extrinsic base;
forming an emitter opening though a center of said non-silicided portion of said extrinsic base;
forming spacers in said emitter opening; and
forming an emitter in said emitter opening, wherein said spacers separate said emitter from silicided portions of said extrinsic base.
12. The method in claim 11 , wherein said process of epitaxially growing said extrinsic base grows polysilicon above said insulator and single crystal silicon above the exposed portions of said intrinsic base.
13. The method in claim 11 , wherein said siliciding process forms said silicided portions of said extrinsic base horizontally adjacent to said non-silicided portion.
14. The method in claim 11 , wherein said spacers are formed on said insulator.