Replacement metal gate FinFET
A method for fabricating a field effect transistor device includes depositing a hardmask over a semiconductor layer depositing a metallic alloy layer over the hardmask, defining a semiconductor fin, depositing a dummy gate stack material layer conformally on exposed portions of the fin, patterning a dummy gate stack by removing portions of the dummy gate stack material using an etching process that selectively removes exposed portions of the dummy gate stack without appreciably removing portions of the metallic alloy layer, removing exposed portions of the metallic alloy layer, forming spacers adjacent to the dummy gate stack, forming source and drain regions on exposed regions of the semiconductor fin, removing the dummy gate stack, removing exposed portions of the metallic alloy layer, and forming a gate stack conformally over exposed portions of the insulator layer and the semiconductor fin.
1. A field effect transistor (FET) device, comprising:
a fin including a semiconductor material arranged on an insulator layer, the fin including a channel region;
a gate stack arranged over the channel region of the fin, the gate stack comprising a gate a dielectric layer;
a hardmask layer disposed on the top surface of the fin, over the channel region, the hardmask layer in contact with the gate stack; and
sidewall spacers adjacent sidewalls of the gate stack, wherein bottom surfaces of the sidewall spacers are separated from a top surface of the fin;
wherein a gap between bottom surfaces of the sidewall spacers and the top surface of the fin is filled by the dielectric layer of the gate stack, and the dielectric layer of the gate stack extends as a continuous liner that lines inner sidewalls of the sidewall spacers, fills the gap between the bottom surfaces of the sidewall spacers and the top surface of the fin, and forms a bottom layer that directly contacts the fin, and
wherein the hardmask layer comprises first and second portions that also fill the gap between a bottom surface of the gate stack contacts and the top surface of the fin.
2. The FET device of claim 1 , wherein the gate stack further comprises a work function metal layer and a metallic gate material.
3. The FET device of claim 1 , wherein the hardmask layer includes an oxide material.
4. The FET device of claim 1 , wherein the sidewall spacers comprise one of an oxide material and a nitride material.