IP Library Granted Patent US 7,504,697
Granted Patent B2
US 7,504,697 · App. 11/965,993 · Granted Mar 17, 2009

Rotational shear stress for charge carrier mobility modification

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Quick Facts
Patent No.
US 7,504,697
App. No.
11/965,993
Granted
Mar 17, 2009
Kind
B2
Abstract

A semiconductor structure and its method of fabrication utilize a semiconductor substrate having an active region mesa surrounded by an isolation trench. A first isolation region having a first stress is located in the isolation trench. A second isolation region having a second stress different than the first stress is also located in the isolation trench. The first isolation region and the second isolation region are sized and positioned to rotationally shear stress the active region mesa.

Claims (20)

1. A semiconductor structure comprising:

a semiconductor substrate having an active region mesa surrounded by an isolation trench;

at least one first isolation region having a first stress located in the isolation trench; and

at least one second isolation region having a second stress different than the first stress also located in the isolation trench, where the first isolation region and the second isolation region are sized and positioned to rotationally shear stress the active region mesa.

2. The semiconductor structure of claim 1 wherein both the first isolation region and the second isolation region contact the active region mesa.

3. The semiconductor structure of claim 1 wherein only one of the first isolation region and the second isolation region contacts the active region mesa.

4. The semiconductor structure of claim 1 wherein the isolation trench is a shallow isolation trench.

5. The semiconductor structure of claim 1 wherein the rotational shear stress is in a clockwise direction.

6. The semiconductor structure of claim 1 wherein the rotational shear stress is in a counter clockwise direction.

7. The semiconductor structure of claim 1 further comprising a semiconductor device located upon the active region mesa.

8. The semiconductor structure of claim 7 wherein the semiconductor device is a field effect transistor.

9. A semiconductor structure comprising:

a semiconductor substrate having an active region mesa surrounded by an isolation trench;

at least one first isolation region having a first stress located in the isolation trench; and

at least one second isolation region having a second stress different than the first stress also located in the isolation trench, where:

the first isolation region and the second isolation region are sized and positioned to rotationally shear stress the active region mesa; and

the first isolation region and the second isolation region are comprised of a same chemical composition.

10. The semiconductor structure of claim 9 wherein the first isolation region and the second isolation region comprise silicon oxide.

11. The semiconductor structure of claim 9 wherein the rotational shear stress is in a clockwise direction.

12. The semiconductor structure of claim 9 wherein the rotational shear stress is in a counter clockwise direction.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 26, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: ELPIS TECHNOLOGIES INC.
Reel/Frame 054528/0023 →