MOSFET with high angle sidewall gate and contacts for reduced miller capacitance
View Patent ↗The present invention relates to an FET device having a conductive gate electrode with angled sidewalls. Specifically, the sidewalls of the FET device are offset from the vertical direction by an offset angle that is greater than about 0° and not more than about 45°. In such a manner, such conductive gate electrode has a top surface area that is smaller than its base surface area. Preferably, the FET device further comprises source/drain metal contacts that are also characterized by angled sidewalls, except that the offset angle of the source/drain metal contacts are arranged so that the top surface area of each metal contact is larger than its base surface area. The FET device of the present invention has significantly reduced gate to drain metal contact overlap capacitance, e.g., less than about 0.07 femtoFarads per micron of channel width, in comparison with conventional FET devices having straight-wall gate electrodes and metal contacts.
1. An FET device comprising:
a semiconductor substrate including source and drain regions;
a gate dielectric layer located on a top surface of the semiconductor substrate; and
a conductive gate electrode located on the gate dielectric layer, wherein said conductive gate electrode has a top, a base, and sidewalls, wherein the sidewalls of said conductive gate electrode are offset from a vertical direction by an offset angle that is greater than about 0° and not more than 30°, so that the top of said conductive gate electrode has a surface area smaller than that of the base.
2. An FET device comprising:
a semiconductor substrate including source and drain regions;
a gate dielectric layer located on a top surface of the semiconductor substrate; and
a conductive gate electrode located on the gate dielectric layer, wherein said conductive gate electrode has a top, a base, and sidewalls, wherein the sidewalls of said conductive gate electrode are offset from a vertical direction by an offset angle that ranges from about 10° to about 20°, so that the top of said conductive gate electrode has a surface area smaller than that of the base.
3. The FET device of claim 2 , further comprising a source extension region and a drain extension region in the semiconductor substrate.
4. The FET device of claim 2 , further comprising a source/drain spacer along each of the sidewalls of the conductive gate electrode.
5. The FET device of claim 2 , further comprising metal silicide conductors for the gate electrode, the source region, and the drain region.
6. The FET device of claim 2 , wherein the conductive gate electrode comprises polysilicon.
7. The FET device of claim 2 , further comprising a capping layer formed over the conductive gate electrode, the source region, and the drain region.
8. The FET device of claim 7 , wherein the capping layer comprises silicon nitride.
9. The FET device of claim 2 , further comprising metal contacts for the source and drain regions, wherein each of said metal contacts has a top, a base, and sidewalls, wherein the sidewalls of each metal contact are offset from a vertical direction by an offset angle that is greater than about 0° and not more than about 45°, so that the top of said metal contact has a surface area larger than that of the base.
10. The FET device of claim 2 , having a gate to drain metal contact overlap capacitance that is less than 0.07 femtoFarads per micron of channel width.
11. An FET device comprising a conductive gate electrode with angled sidewalls that are characterized by an offset angle that is greater than about 0° and not more than 30° with respect to a vertical direction.
12. The FET device of claim 11 , wherein the offset angle ranges from about 10° to about 20°.