Technique for debugging an integrated circuit having a parallel scan-chain architecture
View Patent ↗The present disclosure describes a technique for debugging an integrated circuit having a parallel scan-chain architecture. Blocking circuits are introduced at the inputs and/or outputs of scan-chain branches. The blocking circuits allow the inputs to and/or the outputs from the scan-chain branches to be selectively blocked. This allows individual scan-chain branches to be isolated and debugged.
1. An integrated circuit device comprising:
a plurality of scan-chain branches, each scan-chain branch including a plurality of storage elements;
a plurality of input blocking circuits, each input blocking circuit having an output coupled to a respective input of each scan-chain branch, each input blocking circuit being independently operable to block the input to a respective scan-chain branch;
a plurality of output blocking circuits, each output blocking circuit having a first input coupled to a respective output of each scan-chain branch, each output blocking circuit being independently operable to block the output of a respective scan-chain branch, the plurality of output blocking circuits being selected from the group consisting of a plurality of AND gates and a plurality of OR gates; and
a combiner having a plurality of inputs, each combiner input being coupled to a respective output of each output blocking circuit.
2. The integrated circuit device of claim 1 , wherein the combiner comprises an XOR gate.
3. The integrated circuit device of claim 1 wherein each output blocking circuit includes a second input coupled to a respective control signal line.
4. The integrated circuit device of claim 1 , wherein each input blocking circuit includes a first input coupled to a scan input signal line and each input blocking circuit includes a second input coupled to a respective control signal line.
5. The integrated circuit device of claim 1 , wherein the plurality of input blocking circuits is selected from the group consisting of a plurality of OR gates and a plurality of AND gates.
6. An integrated circuit device comprising:
a plurality of scan-chain branches, each scan-chain branch including a plurality of storage elements; and
a plurality of input blocking circuits, each input blocking circuit having an output coupled to a respective input of each scan-chain branch, each input blocking circuit being independently operable to block the input of a respective scan-chain branch, the plurality of input blocking circuits being selected from the group consisting of a plurality of OR gate and a plurality of AND gates.
7. The integrated circuit device of claim 6 , wherein each input blocking circuit includes a first input coupled to a scan input signal line and each input blocking circuit includes a second input coupled to a respective control signal line.
8. The integrated circuit device of claim 6 , further comprising a plurality of output blocking circuits, each output blocking circuit having a first input coupled to a respective output of each scan-chain branch, each output blocking circuit being independently operable to block the output of a respective scan-chain branch.
9. The integrated circuit device of claim 8 , wherein each output blocking circuit includes a second input coupled to a respective control signal line.
10. The integrated circuit device of claim 8 , further comprising a combiner having a plurality of inputs, each combiner input being coupled to a respective output of each output blocking circuit.
11. The integrated circuit device of claim 8 , wherein the plurality of output blocking circuits is selected from the group consisting of a plurality of AND gates and a plurality of OR gates.
12. A method for debugging an integrated circuit device having a plurality of scan-chain branches, the method comprising:
(1) putting the integrated circuit device in scan mode;
(2) blocking the inputs of all but one of the scan-chain branches;
(3) scanning test data bits in parallel into the plurality of scan-chain branches;
(4) putting the integrated circuit device in capture mode;
(5) operating the integrated circuit device for one or more clock cycles;
(6) putting the integrated circuit device in scan mode;
(7) blocking outputs of all but said one of the scan-chain branches;
(8) scanning a plurality of resulting data bits in parallel out of said one of the scan-chain branches; and
(9) comparing common resulting data bits with a plurality of expected data bits to determine if there are one more faults in the integrated circuit device.
13. The method of claim 12 wherein said blocking the outputs of all but said one of the scan-chain branches comprises:
applying control signals to the inputs of output blocking circuits, the output blocking circuits being selected from the group consisting of a plurality of AND gates and a plurality of OR gates.
14. The method of claim 12 wherein each scan-chain branch includes a plurality of storage elements.
15. The method of claim 12 , wherein said blocking the inputs of all but one of the scan-chain branches comprises:
applying control signals to the inputs of input blocking circuits, the input blocking circuits being selected from the group consisting of a plurality of OR gates and a plurality of AND gates.
16. An integrated circuit device, comprising:
a plurality of scan-chain branches, each scan-chain branch including a plurality of storage elements;
a plurality of input logic gates, each input logic gate having (1) a first input coupled to a scan input signal line, (2) a second input coupled to a respective input control signal line, and (3) an output coupled to an input of a respective scan-chain branch, wherein the plurality of input logic gates is selected from the group consisting of a plurality of OR gates and a plurality of AND gates;
a plurality of output logic gates, each output logic gate having (1) a first input coupled to an output of a respective scan-chain branch and (2) a second input coupled to a respective output control signal line, wherein the plurality of output logic gates is selected from the group consisting of a plurality of AND gates and a plurality of OR gates; and
a combiner having (1) inputs coupled to outputs of the output logic gates and (2) an output coupled to a scan output signal line; wherein the combiner comprises an XOR gate.