Patent Application
Utility
App. No. 10/096,801
· Confirmation No. 8889
FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND TESTING METHOD
Inventor:
Tomohiro Taira
Patent Expired Due to NonPayment of Maintenance Fees Under 37 CFR 1.362
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2003-08-08 | IFEE |
Issue Fee Payment (PTO-85B) | 1 | View | |
| 2002-03-14 | TRNA |
Transmittal of New Application | 2 | View | |
| 2002-03-14 | SPEC |
Specification | 40 | View | |
| 2002-03-14 | CLM |
Claims | 6 | View | |
| 2002-03-14 | ABST |
Abstract | 1 | View | |
| 2002-03-14 | DRW |
Drawings-only black and white line drawings | 13 | View | |
| 2002-03-14 | OATH |
Oath or Declaration filed | 3 | View |
Inventors
Tomohiro Taira
Chitose, JAPAN
Attorneys & Agents of Record
Classification
USPC
438/17
G01R31/287
H10P74/23
G01R31/2831
Prosecution
- Examiner
- STEVENSON, ANDRE C
- Art Unit
- 2899
- Customer No.
- 20457
- Docket No.
- 501.41197X00
- Confirmation No.
- 8889
Foreign Priority
2001-075671
·
2001-03-16
·
JAPAN
Publication
- Pub. No.
- US20020132381A1
- Pub. Date
- 2002-09-19
Patent Term Adjustment
-30days
from
HITACHI, LTD.
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2003-09-26
from
TAIRA, TOMOHIRO
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2002-03-14
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Quick Facts
- App. No.
- 10/096,801
- Filed
- 2002-03-14
- Granted
- 2003-10-28
- Pub. No.
- US20020132381A1
- Examiner
- STEVENSON, ANDRE C
- Art Unit
- 2899
- PTA
- -30 days
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