IP Library Granted Patent US 6,785,870
Granted Patent Utility
US 6,785,870 · Confirmation No. 9157

METHOD OF OPTIMIZING HIGH PERFORMANCE CMOS INTEGRATED CIRCUIT DESIGNS FOR POWER CONSUMPTION AND SPEED USING GLOBAL AND GREEDY OPTIMIZATIONS IN COMBINATION

Inventor: Thomas W. Chen
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2004-05-05 892 List of references cited by examiner 1 View
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2002-03-14 TRNA Transmittal of New Application 1 View
2002-03-14 SPEC Specification 17 View
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Quick Facts
Patent No.
US 6,785,870
App. No.
10/098,110
Filed
2002-03-14
Granted
2004-08-31
Pub. No.
US20030177452A1
Examiner
DINH, PAUL
Art Unit
2825
PTA
-44 days