IP Library › Granted Patent US 6,687,888
Granted Patent Utility
US 6,687,888 · Confirmation No. 9152

METHOD OF OPTIMIZING HIGH PERFORMANCE CMOS INTEGRATED CIRCUIT DESIGNS FOR POWER CONSUMPTION AND SPEED

Inventor: Thomas W. Chen
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2002-03-14 TRNA Transmittal of New Application 1 View
2002-03-14 SPEC Specification 18 View
2002-03-14 CLM Claims 4 View
2002-03-14 ABST Abstract 1 View
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Quick Facts
Patent No.
US 6,687,888
App. No.
10/098,111
Filed
2002-03-14
Granted
2004-02-03
Pub. No.
US20030177459A1
Examiner
DO, THUAN V
Art Unit
2825
PTA
-63 days