IP Library › Granted Patent US 6,711,720
Granted Patent Utility
US 6,711,720 · Confirmation No. 1133

METHOD OF OPTIMIZING HIGH PERFORMANCE CMOS INTEGRATED CIRCUIT DESIGNS FOR POWER CONSUMPTION AND SPEED THROUGH GENETIC OPTIMIZATION

Inventor: Thomas W. Chen
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2004-01-21 IFEE Issue Fee Payment (PTO-85B) 1 View
2003-09-03 IDS Information Disclosure Statement (IDS) Form (SB08) 3 View
2002-03-14 TRNA Transmittal of New Application 1 View
2002-03-14 SPEC Specification 17 View
2002-03-14 CLM Claims 4 View
2002-03-14 ABST Abstract 1 View
2002-03-14 DRW Drawings-only black and white line drawings 5 View
2002-03-14 OATH Oath or Declaration filed 1 View
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Quick Facts
Patent No.
US 6,711,720
App. No.
10/098,136
Filed
2002-03-14
Granted
2004-03-23
Pub. No.
US20030177453A1
Examiner
SIEK, VUTHE
Art Unit
2825
PTA
0 days