Granted Patent
Utility
US 6,545,321
· Confirmation No. 2000
ESD PROTECTION CIRCUIT FOR A SEMICONDUCTOR INTEGRATED CIRCUIT
Inventor:
Yasuyuki Morishita
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⬇ PDF
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2002-03-15 | TRNA |
Transmittal of New Application | 2 | View | |
| 2002-03-15 | SPEC |
Specification | 43 | View | |
| 2002-03-15 | CLM |
Claims | 5 | View | |
| 2002-03-15 | ABST |
Abstract | 1 | View | |
| 2002-03-15 | DRW |
Drawings-only black and white line drawings | 26 | View | |
| 2002-03-15 | OATH |
Oath or Declaration filed | 1 | View |
Inventors
Yasuyuki Morishita
Tokyo, JAPAN
Attorneys & Agents of Record
Classification
USPC
257/355
H10D89/713
Prosecution
- Examiner
- FARAHANI, DANA
- Art Unit
- 2814
- Customer No.
- 26304
- Docket No.
- NECF 19.555
- Confirmation No.
- 2000
Foreign Priority
2001-078195
·
2001-03-19
·
JAPAN
2001-335348
·
2001-10-31
·
JAPAN
2002-063771
·
2002-03-08
·
JAPAN
Publication
- Pub. No.
- US20020130366A1
- Pub. Date
- 2002-09-19
Patent Term Adjustment
0days
No related applications found.
CHANGE OF ADDRESS
Recorded 2017-11-29
from
NEC CORPORATION
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2003-02-19
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Quick Facts
- Patent No.
- US 6,545,321
- App. No.
- 10/099,708
- Filed
- 2002-03-15
- Granted
- 2003-04-08
- Pub. No.
- US20020130366A1
- Examiner
- FARAHANI, DANA
- Art Unit
- 2814
- PTA
- 0 days
External Links