Reference cells for TCCT based memory cells
View Patent ↗A reference cell produces a reference current that is about half of the current produced by a memory cell. The reference cell is essentially the same as the memory cell with an additional current reduction device that can be a transistor. Adjusting a reference voltage applied to the transistor allows the reference current to be varied. A control circuit to produce the reference voltage includes dedicated memory and reference cells and a feedback circuit that compares the two cells' currents. The feedback circuit applies the reference voltage to the reference cell of the control circuit and adjusts the reference voltage until the current from the reference cell is about half of the current from the memory cell. The reference voltage is then applied to other reference cells in a memory array.
1. A circuit to generate a reference voltage, comprising:
a memory cell configured to generate a first current;
a reference cell configured to generate a second currant; and
a feedback circuit configured to
compare the first current to the second current, and
generate a reference voltage in response thereto;
wherein the reference cell is configured to receive the reference voltage.
2. The circuit of claim 1 wherein the second current varies as a function of the reference voltage.
3. The circuit of claim 2 wherein the reference cell includes a pass transistor configured to receive the reference voltage.
4. The circuit of claim 3 wherein the memory cell includes a pass transistor having a first W/L ratio.
5. The circuit of claim 4 wherein the pass transistor of the reference cell has a second W/L ratio equal to about twice the first W/L ratio.
6. A circuit to generate a reference voltage, comprising:
a memory cell configured to generate a first current;
a first reference cell configured to generate a second current;
a second reference cell configured to generate a third current; and
a feedback circuit configured to
compare the first current to the sum of the second and third currents, and
generate a reference voltage in response thereto.
7. The circuit of claim 6 wherein the first and second reference cells are each configured to receive the reference voltage.
8. The circuit of claim 7 wherein the second and third currents vary as a function of the reference voltage.
9. The circuit of claim 6 wherein the memory cell is a TCCT based memory cell and includes an NDR device coupled to a first pass transistor.
10. The circuit of claim 6 wherein multiple memory cells generate the first current, multiple first reference cells generate the second current, and multiple second reference cells generate the third current.
11. The circuit of claim 6 wherein the first and second reference cells each include
an NDR device,
a first pass transistor coupled to the NDR device, and
a second pass transistor coupled to the first pass transistor.
12. The circuit of claim 11 wherein each second pass transistor has a gate configured to receive the reference voltage.
13. The circuit of claim 12 wherein the feedback circuit maintains the sum of the second and third currents equal to the first current by adjusting the reference voltage.
14. The circuit of claim 6 wherein the feedback circuit includes a current comparator coupled to a ramp output voltage generator.
15. The circuit of claim 6 wherein the memory cell is an SRAM cell that includes a pass transistor.
16. The circuit of claim 6 wherein the memory cell is a floating gate based memory cell that includes a pass transistor.
17. The circuit of claim 6 wherein the memory cell is an MRAM cell that includes a pass transistor.
18. A circuit to generate a reference voltage to control a current output of a reference cell, comprising:
a TCCT based memory cell including an NDR device and configured to generate a first current;
a first reference cell configured to generate a second current and including
an NDR device, and
a pass transistor coupled to the NDR device;
a second reference cell configured to generate a third current and including
an NDR device, and
a pass transistor coupled to the NDR device; and
a feedback circuit configured to
compare the first current to the sum of the second and third currents, and
generate a reference voltage in response thereto.
19. The circuit of claim 18 wherein the pass transistors of the first and second reference cells each have a gate configured to receive the reference voltage.
20. The circuit of claim 19 wherein the feedback circuit maintains the sum of the second and third currents equal to the first current by adjusting the reference voltage.
21. The circuit of claim 20 wherein the feedback circuit maintains the sum of the currents from more than two memory elements equal to the first current by adjusting the reference voltage.
22. The circuit of claim 18 wherein the feedback circuit includes a current comparator coupled to a ramp output voltage generator.