Method and apparatus for cycle-based computation

1. A computer system for cycle-based computation, comprising:

a processor array;

a translation component adapted to translate a cycle-based design;

a host computer operatively connected to the processor array and to the translation component;

a data connection component interconnecting a plurality of members of the processor array using static routing, wherein the data connection component comprises a plurality of levels, wherein each member of the plurality of levels contains a routing processor to perform static routing;

a synchronization component enabling known timing relationships among the plurality of members of the processor array;

a host service request component adapted to send a host service request from a member of the processor array to the host computer; and

an access component adapted to access a portion of a state of the processor array and a portion of a state of the data connection.

2. The computer system of claim 1 , wherein the cycle-based design is translated into execution processor code, routing processor code, and control code.

3. The computer system of claim 1 , wherein the cycle-based design comprises a plurality of simulation instructions written in a computer readable language.

4. The computer system of claim 3 , wherein the plurality of simulation instructions comprises a design logic instruction translated from hardware description language source code.

5. The computer system of claim 3 , wherein the plurality of simulation instructions comprises a design logic instruction translated from Verilog source code.

6. The computer system of claim 3 , wherein the plurality of simulation instructions comprises a design logic instruction translated from register transfer level source code.

7. The computer system of claim 3 , wherein the computer readable language is a hardware description language.

8. The computer system of claim 3 , wherein the computer readable language is a high level computer programming language.

9. The computer system of claim 1 , wherein the access component comprises a computer network operatively connected to the host computer and to the data connection component.

10. The computer system of claim 1 , wherein the access component comprises a broadcast tree and a reply tree.

11. The computer system of claim 1 , wherein the host service request component comprises a control tree and an attention tree.

12. The computer system of claim 1 , wherein the member of the processor array is capable of multiple-bit calculations.

13. The computer system of claim 1 , wherein the member of the processor array has memory resources.

14. The computer system of claim 1 , wherein the member of the processor array is capable of executing custom instructions.

15. The computer system of claim 1 , wherein static routing is scheduled prior to execution of cycle-based computation.

16. The computer system of claim 1 , wherein the data connection component comprises a plurality of levels, wherein each member of the plurality of levels contains a crossbar switch.

17. The computer system of claim 1 , wherein the data connection component enables expansion of the processor array.

18. The computer system of claim 1 , wherein the data connection component comprises a register file unit storage memory.

19. The computer system of claim 1 , wherein the data connection component comprises a global control register file unit storage memory.

20. The computer system of claim 1 , wherein the data connection component comprises an input output buffer.

21. The computer system of claim 1 , wherein the data connection component comprises a backplane connecting a plurality of system boards.

22. The computer system of claim 1 , wherein a message is routed to the member of the processor array using the data connection component.

23. The computer system of claim 22 , wherein the message comprises a tag identifier for identifying the message to the member of the processor array.

24. The computer system of claim 23 , wherein the tag identifier is statically assigned.

25. The computer system of claim 23 , wherein the tag identifier is checked by the data connection component to ensure timing correctness of message delivery.

26. The computer system of claim 23 , wherein the tag identifier is checked by the data connection component to determine a correct routing of the message.

27. The computer system of claim 1 , wherein the access component does not require execution of execution processor code by the member of the processor array.

28. The computer system of claim 1 , wherein the access component does not require execution of routing processor code by a routing processor.

29. The computer system of claim 1 , wherein the access component supports reading from and writing to the state of the processor array by the host computer.

30. The computer system of claim 1 , wherein the host service request comprises a request for a cycle-based designing language interface call.

31. The computer system of claim 1 , wherein the host service request comprises a request for an input/output call.

32. The computer system of claim 1 , wherein the host service request comprises a request for an interrupt.

33. The computer system of claim 1 , wherein the routing processor specifies message routing connections.

34. The computer system of claim 1 , further comprising:

a loading mechanism to load the execution processor code onto the processor array from the host computer.

35. The computer system of claim 1 , further comprising:

a callback mechanism enabling a portion of the cycle-based computation to be performed on the host computer.

36. The computer system of claim 1 , further comprising:

a plurality of simulation domains.

37. The computer system of claim 36 , wherein the plurality of simulation domains are divided by a simulation domain boundary.

38. A computer system for cycle-based computation, comprising:

a processor array;

a translation component adapted to translate a cycle-based design;

a host computer operatively connected to the processor array and to the translation component;

a data connection component interconnecting a plurality of members of the processor array using static routing, wherein the data connection component comprises a plurality of levels, wherein each member of the plurality of levels contains a routing processor to perform static routing;

a synchronization component enabling known timing relationships among the plurality of members of the processor array;

a host service request component adapted to send a host service request from a member of the processor array to the host computer;

an access component adapted to access a portion of a state of the processor array and a portion of a state of the data connection;

a loading mechanism to load the execution processor code onto the processor array from the host computer;

a callback mechanism enabling a portion of the cycle-based computation to be performed on the host computer; and

a plurality of simulation domains.

39. A method for performing computation on a cycle-based computing environment, comprising:

translating a cycle-based design into cycle-based computation code;

executing the cycle-based computation code on a member of a processor array to generate a message;

statically routing the message along a data connection component, wherein the data connection component comprises a plurality of levels, wherein each member of the plurality of levels contains a routing processor to perform static routing;

synchronizing execution of the cycle-based computation code;

sending a host service request from the member of the processor array to a host computer; and

accessing a portion of a state of the processor array and a portion of a state of a data connection component.

40. The method of claim 39 , wherein the cycle-based computation code comprises:

an execution processor code; a static routing code; and a control code.

41. The method of claim 40 , further comprising:

executing the control code on a host interface to interface the host computer with the processor array.

42. The method of claim 40 , further comprising:

loading the execution processor code and the static routing code onto the processor array.

43. The method of claim 39 , wherein executing the cycle-based computation code is performed on a plurality of simulation domains.

44. The method of claim 39 , wherein the cycle-based design comprises a plurality of simulation instructions written in a computer readable language.

45. The method of claim 39 , further comprising:

executing a portion of the cycle-based design on the host computer.

46. The method of claim 39 , further comprising:

responding to the host service request.

47. A method for performing computation on a cycle-based computing environment, comprising:

translating a cycle-based design into cycle-based computation code;

executing the cycle-based computation code on a member of a processor array to generate a message;

statically routing the message along a data connection component, wherein the data connection component comprises a plurality of levels, wherein each member of the plurality of levels contains a routing processor to perform static routing;

synchronizing execution of the cycle-based computation code;

sending a host service request from the member of the processor array to a host computer;

accessing a portion of a state of the processor array and a portion of a state of a data connection component;

executing a portion of the cycle-based design on the host computer;

responding to the host service request.

48. A method of preparing a cycle-based design for simulation, comprising:

verifying a design standard of the cycle-based design using a style checker to generate a verified cycle-based design;

compiling the verified cycle-based design to produce execution processor code and a routing table; and

producing a simulation by executing the execution processor code on a member of a processor array;

wherein the simulation uses the routing table to statically route a message to the member of the processor array along a data connection component, wherein the data connection component comprises a plurality of levels, wherein each member of the plurality of levels contains a routing processor to perform static routing.

49. The method of claim 48 , wherein the step of compiling the verified cycle-based design comprises producing an annotated symbol table.

50. The method of claim 48 , wherein the step of compiling the verified cycle-based design comprises producing control code.

51. The method of claim 48 , wherein the step of compiling the verified cycle-based design comprises producing execution processor code targeted to a specific environment.

52. A method of synchronizing cycle-based computation on a processor array, comprising:

executing execution processor code on the processor array;

detecting a value of a run bit associated with a member of the processor array;

halting execution of execution processor code on the processor array if a host service request from the member of the processor array is detected; and

resuming execution of execution processor code on the processor array if the value of the run bit has a predetermined value, and the host service request from the member of the processor array is not detected;

wherein execution of execution processor code uses a statically routed message to the member of the processor array along a data connection component, wherein the data connection component comprises a plurality of levels, wherein each member of the plurality of levels contains a routing processor to perform static routing.

53. The method of claim 52 , further comprising:

polling the member of the processor array to detect the host service request from the member of the processor array.

54. The method of claim 52 , further comprising:

polling the member of the processor array to detect a reply tree message from the member of the processor array.

55. The method of claim 52 , further comprising:

resuming execution of execution processor code on the processor array if the value of the run bit has a predetermined value, and a reply tree message from the member of the processor array is not detected.

56. A method of synchronizing cycle-based computation on a processor array, comprising:

executing execution processor code on the processor array;

detecting a value of a run bit associated with a member of the processor array;

halting execution of execution processor code on the processor array if a host service request from the member of the processor array is detected;

resuming execution of execution processor code on the processor array if the value of the run bit has a predetermined value, and the host service request from the member of the processor array is not detected;

polling the member of the processor array to detect the host service request from the member of the processor array;

polling the member of the processor array to detect a reply tree message from the member of the processor array; and

resuming execution of execution processor code on the processor array if the value of the run bit has a predetermined value, and a reply tree message from the member of the processor array is not detected,

wherein execution of execution processor code uses a statically routed message to the member of the processor array along a data connection component, wherein the data connection component comprises a plurality of levels, wherein each member of the plurality of levels contains a routing processor to perform static routing.

57. An apparatus for performing computation on a cycle-based computing environment, comprising:

means for translating a cycle-based design into cycle-based computation code;

means for executing the cycle-based computation code on a member of a processor array to generate a message;

means for statically routing the message along a data connection component;

means for synchronizing execution of the cycle-based computation code;

means for sending a host service request from the member of the processor array to a host computer; and

means for accessing a portion of a state of the processor array and a portion of a state of a data connection component,

wherein the data connection component comprises a plurality of levels, wherein each member of the plurality of levels contains a routing processor to perform static routing.

58. An apparatus for preparing a cycle-based design for simulation, comprising:

means for verifying a design standard of the cycle-based design using a style checker to generate a verified cycle-based design;

means for compiling the verified cycle-based design to produce execution processor code and a routing table; and

means for producing a simulation by executing the execution processor code on a member of a processor array;

wherein the simulation uses the routing table to statically route a message to the member of the processor array along a data connection component, wherein the data connection component comprises a plurality of levels, wherein each member of the plurality of levels contains a routing processor to perform static routing.

59. An apparatus for synchronizing cycle-based computation on a processor array, comprising:

means for executing execution processor code on the processor array;

means for detecting a value of a run bit associated with a member of the processor array;

means for halting execution of execution processor code on the processor array if a host service request from the member of the processor array is detected; and

means for resuming execution of execution processor code on the processor array if the value of the run bit has a predetermined value, and the host service request from the member of the processor array is not detected,

wherein execution of execution processor code uses a statically routed message to the member of the processor array along a data connection component, wherein the data connection component comprises a plurality of levels, wherein each member of the plurality of levels contains a routine processor to perform static routing.