Method of communicating between modules in a decoding system

1. A decoding system comprising:

a core decoder processor adapted to perform decoding functions on a coded data stream and adapted to issue commands to an entropy decoding accelerator; and

an entropy decoding accelerator adapted to receive commands from the core decoder processor and to perform entropy decoding operations on entropy-coded code in the data stream in response to said commands, wherein the entropy decoding accelerator is adapted to provide a command status signal to the core decoder processor, the command status signal indicating whether or not a command is completed;

wherein the core decoder processor is adapted to issue a register-read instruction to the entropy decoding accelerator that causes the contents of a register in the entropy decoding accelerator to be provided to the core decoder processor, wherein if the command status signal indicates that a previous command is not yet completed when a register-read instruction is issued by the core decoder processor, the contents of the register in the entropy decoder are not provided to the core decoder processor until the command status signal indicates that the previous command is completed.

2. The system of claim 1 wherein the entropy decoding accelerator comprises a command status register that indicates whether or not a command is completed and wherein the core decoder processor is adapted to poll the command status register to determine if the command is completed.

3. The system of claim 2 wherein the core decoder processor does not issue a new command to the entropy decoder accelerator unless the command status register indicates that a previous command is completed.

4. The system of claim 1 wherein the register-read instruction includes a wait bit, wherein if the wait bit is set and the command status signal indicates that a previous command is not yet completed when a register-read instruction is issued by the core decoder processor, the contents of the register in the entropy decoder are not provided to the core decoder processor until the command status signal indicates that the previous command is completed, but wherein if the wait bit is not set and a register-read instruction is issued by the core decoder processor, the contents of the register in the entropy decoder are provided to the core decoder processor regardless of the value of the command status signal.

5. The system of claim 1 wherein the core decoder processor is adapted to perform decoding functions on a coded media data stream and the entropy decoding accelerator is adapted to perform entropy decoding operations on entropy-coded code in the media data stream.

6. The system of claim 1 wherein the core decoder processor is adapted to perform decoding functions on a coded video data stream and the entropy decoding accelerator is adapted to perform entropy decoding operations on entropy-coded code in the video data stream.

7. The decoding system of claim 1 wherein the entropy decoding accelerator is a variable-length decoding accelerator adapted to perform variable-length decoding operations on variable-length code in the data stream in response to said commands.

8. The decoding system of claim 1 wherein the entropy decoding accelerator is adapted to perform entropy decoding operations on single-syntax elements in the data stream in response to said commands.

9. The decoding system of claim 1 wherein the entropy decoding accelerator is adapted to perform entropy decoding operations on complete blocks of syntax elements in the data stream in response to said commands.

10. The decoding system of claim 9 wherein the entropy decoding accelerator is adapted to concurrently perform entropy decoding operations on single-syntax elements and complete blocks of single-syntax elements in the data stream in response to said commands.

11. The decoding system of claim 1 wherein the entropy decoding accelerator is adapted to perform entropy decoding operations on single-syntax elements and on complete blocks of syntax elements in the data stream in response to said commands.

12. A method of controlling first and second decoding accelerators coupled to a core decoder processor adapted to decode a data stream, the first and second accelerators adapted to assist the core decoder processor with first and second decoding functions respectively, the method comprising:

(a) providing, with the core decoder processor, first and second commands to the first and second accelerators respectively via posted write operations; and

(b) polling the first and second accelerators with the core decoder processor to determine whether first and second operations, corresponding to the first and second commands respectively, have been performed by the first and second accelerators respectively.

13. The method of claim 12 wherein the first and second commands instruct the first and second accelerators to perform the first and second decoding functions and wherein polling step (b) comprises polling the first and second accelerators with the core decoder processor to determine whether the first and second decoding functions have been completed.

14. The method of claim 12 further comprising a step (c), performed after providing step (a) and prior to polling step (b), of performing a third decoding function with the core decoder processor.

15. The method of claim 12 wherein providing step (a) comprises:

(a)(i) providing the first and second commands to an intermediate storage element; and

(a)(ii) writing the first and second commands to the first and second accelerators when both the first and second accelerators are ready to receive the commands.

16. The method of claim 15 wherein step (a)(ii) is performed a plurality of core decoder clock cycles after step (a)(i) is performed.

17. The method of claim 12 further comprising a step (c), after step (b), of:

(c) after the core decoder processor determines, via its polling of the first and second accelerators, that the operations corresponding to the first and second commands have been performed, providing, with the core decoder processor, third and fourth commands to the first and second accelerators, respectively, via posted write operations.

18. The method of claim 12 further comprising a step (c), after step (b), of:

(c) after the core decoder processor determines, via its polling of the first and second accelerators, that the first and second operations have been performed by the first and second accelerators, providing, with the core decoder processor, third and fourth commands to the first and second accelerators respectively, via posted write operations.

19. The method of claim 18 wherein the second decoding function, performed by the second accelerator, depends on a product previously produced by the first decoding function, performed by the first accelerator.

20. A decoding system comprising:

a core decoder processor adapted to perform decoding functions on a coded data stream and having a co-processor interface, the co-processor interface including a co-processor status register adapted to receive a status of a co-processor; and

a first decoding accelerator adapted to assist the core decoder processor with a first decoding function and coupled to the core decoder processor via the co-processor interface, wherein the first decoding accelerator is adapted to provide status data indicative of a status of the first accelerator to the co-processor status register; and

a second decoding accelerator adapted to assist the core decoder processor with a second decoding function, wherein the second decoding accelerator is adapted to provide status data indicative of a status of the second accelerator to the co-processor status register;

wherein each of the first and second decoding accelerators are assumed a set of bit positions in the co-processor status register.

21. The system of claim 20 wherein the core decoder processor is adapted to issue commands to the first and second decoding accelerators and wherein the first and second decoding accelerators are adapted to provide status data indicative of whether a command is completed to the co-processor status register.

22. The system of claim 20 further comprising:

a third decoding accelerator adapted to assist the core decoder processor with a third decoding function, wherein the third decoding accelerator is adapted to provide status data indicative of a status of the third accelerator to the co-processor status register.

23. The system of claim 20 further comprising:

a data bus coupled to the co-processor interface and to the first and second decoding accelerators, wherein each of the first and second accelerators are adapted to provide status data to the bit positions of the data bus that correspond to the bit positions assigned each accelerator in the co-processor status register, and wherein the co-processor interface is adapted to read the contents of the data bus into the co-processor status register.

24. A decoding system comprising:

a core decoder processor adapted to perform decoding functions on a coded data stream and having a co-processor interface, the co-processor interface including a co-processor status register adapted to receive a status of a co-processor;

an entropy decoding accelerator adapted to perform entropy decoding operations on entropy-coded code in the data stream and coupled to the core decoder processor via the co-processor interface, wherein the entropy decoding accelerator is adapted to provide status data indicative of a status of the entropy decoding accelerator to the co-processor status register; and

a second decoding accelerator adapted to assist the core decoder processor with a second decoding function, wherein the second decoding accelerator is adapted to provide status data indicative of a status of the second accelerator to the co-processor status register.

25. A decoding system comprising:

a core decoder processor adapted to perform decoding functions on a coded data stream and having a co-processor interface, the co-processor interface including a co-processor status register adapted to receive a status of a co-processor;

a first decoding accelerator adapted to assist the core decoder processor with a first decoding function and coupled to the core decoder processor via the co-processor interface, wherein the entropy decoding accelerator is adapted to provide status data indicative of a status of the entropy decoding accelerator to the co-processor status register; and

a second decoding accelerator adapted to assist the core decoder processor with a second decoding function, wherein the second decoding accelerator is adapted to provide status data indicative of a status of the second accelerator to the co-processor status register, wherein the second decoding accelerator comprises one of an inverse quantizer, an inverse transform module, a pixel filter, a motion compensation module and a deblocking filter.

26. A decoding system comprising:

a core decoder processor adapted to perform decoding functions on a coded data stream and having a co-processor interface, the co-processor interface including a co-processor status register adapted to receive a status of a co-processor;

a first decoding accelerator adapted to assist the core decoder processor with a first decoding function and coupled to the core decoder processor via the co-processor interface, wherein the entropy decoding accelerator is adapted to provide status data indicative of a status of the entropy decoding accelerator to the co-processor status resister; and

a second decoding accelerator adapted to assist the core decoder processor with a second decoding function, wherein the second decoding accelerator is adapted to provide status data indicative of a status of the second accelerator to the co-processor status register and wherein the second decoding accelerator is coupled to the core decoder processor via an interface other than the co-processor interface.