Granted Patent
Utility
US 6,684,371
· Confirmation No. 2152
LAYOUT OF SEMICONDUCTOR INTEGRATED CIRCUIT
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⬇ PDF
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2003-12-15 | IFEE |
Issue Fee Payment (PTO-85B) | 1 | View | |
| 2002-04-08 | TRNA |
Transmittal of New Application | 2 | View | |
| 2002-04-08 | ADS |
Application Data Sheet | 1 | View | |
| 2002-04-08 | SPEC |
Specification | 15 | View | |
| 2002-04-08 | CLM |
Claims | 3 | View | |
| 2002-04-08 | ABST |
Abstract | 1 | View | |
| 2002-04-08 | DRW |
Drawings-only black and white line drawings | 8 | View |
Inventors
Attorneys & Agents of Record
Classification
USPC
716/1
G06F30/39
H10D89/00
H10W72/932
Prosecution
- Examiner
- DINH, PAUL
- Art Unit
- 2825
- Customer No.
- 32628
- Docket No.
- D-1255
- Confirmation No.
- 2152
Foreign Priority
2001-114331
·
2001-04-12
·
JAPAN
Publication
- Pub. No.
- US20020152448A1
- Pub. Date
- 2002-10-17
Patent Term Adjustment
0days
No related applications found.
MERGER AND CHANGE OF NAME
Recorded 2011-08-26
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2010-04-20
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2002-06-07
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Quick Facts
- Patent No.
- US 6,684,371
- App. No.
- 10/117,340
- Filed
- 2002-04-08
- Granted
- 2004-01-27
- Pub. No.
- US20020152448A1
- Examiner
- DINH, PAUL
- Art Unit
- 2825
- PTA
- 0 days
External Links