Graphical loop profile analysis
View Patent ↗A tool is disclosed that allows a hardware designer using a behavioral synthesis tool to view a calculated execution time for a group of related loops identified in source code describing a hardware design circuit. Further, a designer can then interactively unroll and/or pipeline a selected loop without having to modify the source code description of the circuit. Using a graphical user interface (GUI), the designer can modify the loop design easily and see the results of the new loop configuration without having to generate the RTL code, perform RTL synthesis, etc. For example, the designer can readily view the relative loop execution time of the circuit to better determine whether the design is acceptable. Additionally, the designer can execute an area-versus-latency analysis, and, if the analysis is not satisfactory, the designer can unroll and or pipeline selected loops using the GUI.
1. In a behavioral synthesis tool used to design a hardware circuit, a method comprising:
identifying loops within a source code representation of a hardware circuit;
calculating an estimate of hardware execution time for the identified loops; and
displaying the estimate of hardware execution time in association with the identified loops, wherein the displayed execution time for a parent loop is represented as a bar graph, and the bar graph of the parent loop represents the execution time of a child loop as a different shade or color.
2. The method of claim 1 , further comprising:
receiving via a graphical user interface, an indication to unroll a specified loop;
unrolling the specified loop;
calculating the execution time for the unrolled loop; and
displaying the execution time associated with the loops including the unrolled loop.
3. The method of claim 2 , wherein unrolling means unrolling without changing the source code.
4. The method of claim 2 , wherein an integrated circuit is created containing the unrolled loop.
5. The method of claim 1 , further comprising:
receiving via a graphical user interface, an indication to pipeline a specified loop;
pipelining the specified loop;
calculating the execution time for the pipelined loop; and
displaying the execution time associated with the loops including the pipelined loop.
6. The method of claim 5 , wherein pipelining means pipelining without changing the source code.
7. The method of claim 1 , wherein the displayed execution time for the identified loops is represented as relative to the execution time of the other identified loops.
8. The method of claim 1 , wherein calculating comprises:
for each loop, summing the time required to complete the hardware instructions within the loop; and
multiplying the time required to complete the hardware instructions within a loop by the number of iterations of the loop.
9. The method of claim 1 , wherein identifying means reading loop directive identifiers in the source code.
10. In a behavioral synthesis tool used to design a hardware circuit, a method comprising:
identifying loops within a source code representation of a hardware circuit;
calculating an estimate of hardware execution time for the identified loops; and
displaying the estimate of hardware execution time in association with the identified loops, wherein the displayed execution time for a loop is represented as a bar, and the bar represents the execution time in the loop as a shade or color, and the bar represents the execution time of a descendent loop as a different shade or color.
11. In a behavioral synthesis tool used to design a hardware circuit, a method comprising:
identifying loops within a source code representation of a hardware circuit;
calculating an estimate of hardware execution time for the identified loops; and
displaying the estimate of hardware execution time in association with the identified loops, wherein the displayed execution time for the loops are a bar graph, and a bar representing a parent loop is greater than or equal to the sum of the bars representing its child loops.
12. The method of claim 11 , further comprising:
receiving via a graphical user interface, an indication to unroll a specified loop;
unrolling the specified loop;
calculating the execution time for the unrolled loop; and
displaying the execution time associated with the loops including the unrolled loop.
13. The method of claim 12 , wherein unrolling means unrolling without changing the source code.
14. The method of claim 12 , wherein an integrated circuit is created containing the unrolled loop.
15. The method of claim 11 , further comprising:
receiving via a graphical user interface, an indication to pipeline a specified loop;
pipelining the specified loop;
calculating the execution time for the pipelined loop; and
displaying the execution time associated with the loops including the pipelined loop.
16. The method of claim 15 , wherein pipelining means pipelining without changing the source code.
17. The method of claim 11 , wherein the displayed execution time for the identified loops is represented as relative to the execution time of the other identified loops.
18. The method of claim 11 , wherein calculating comprises:
for each loop, summing the time required to complete the hardware instructions within the loop; and
multiplying the time required to complete the hardware instructions within a loop by the number of iterations of the loop.
19. The method of claim 11 , wherein identifying means reading loop directive identifiers in the source code.
20. In a behavioral synthesis tool used to design a hardware circuit, a method comprising:
identifying loops within a source code representation of a hardware circuit;
calculating an estimate of hardware execution time for the identified loops; and
displaying the estimate of hardware execution time in association with the identified loops, wherein calculating comprises:
assigning hardware instructions within a loop to clock cycles within a loop thereby obtaining a number of clock cycles within the loop;
for non-pipelined loops, using the following equation: (number of clock cycles within the loop*number of loop iterations); and
for pipelined loops, using the following equation: (number of clock cycles within the loop+(initiation interval*(number of loop iterations −1))), wherein the initiation interval comprises a number of clock cycles before the pipelined loops process new input data.
21. In a behavioral synthesis tool used to design a hardware circuit, a method comprising:
identifying loops within a source code representation of a hardware circuit;
calculating an estimate of hardware execution time for the identified loops; and
displaying the estimate of hardware execution time in association with the identified loops, wherein the displayed estimate of hardware execution time is within an interactive graphical user interface which includes a representation of hardware operations within loops, and a loop-only button removes hardware operations from the representation.
22. In a behavioral synthesis tool used to design a hardware circuit, a method comprising:
identifying loops within a source code representation of a hardware circuit;
calculating an estimate of hardware execution time for the identified loops, wherein calculating comprises:
assigning hardware instructions within a loop to clock cycles within a loop thereby obtaining a number of clock cycles within the loop;
for non-pipelined loops, using the following equation: (number of clock cycles within the loop*number of loop iterations); and
for pipelined loops, using the following equation: (number of clock cycles within the loop+(initiation interval*(number of loop iterations −1))), wherein the initiation interval comprises a number of clock cycles before the pipelined loops process new input data; and
displaying the estimate of hardware execution time in association with the identified loops, wherein the displayed execution time for the loops is represented as a bar graph, a pie graph, a numeric graph, a graphic comparison or a numeric comparison.
23. The method of claim 22 , wherein the displayed execution time for the identified loops is represented as relative to the execution time of the other identified loops.
24. The method of claim 22 , wherein calculating comprises:
for each loop, summing the time required to complete the hardware instructions within the loop; and
multiplying the time required to complete the hardware instructions within a loop by the number of iterations of the loop.
25. The method of claim 22 , wherein the act of identifying loops comprises reading loop directive identifiers in the source code.
26. In a behavioral synthesis tool used to design a hardware circuit, a method comprising:
identifying loops within a source code representation of a hardware circuit;
calculating an estimate of hardware execution time for the identified loops; and
displaying the estimate of hardware execution time in association with the identified loops, wherein the displayed execution time for the loops is represented as a bar graph, a pie graph, a numeric graph, a graphic comparison or a numeric comparison, wherein the displayed execution time for a parent loop is represented as a bar graph, and the bar graph of the parent loop represents the execution time of a child loop as a different shade or color.
27. The method of claim 26 , wherein the displayed execution time for the identified loops is represented as relative to the execution time of the other identified loops.
28. The method of claim 26 , wherein calculating comprises:
for each loop, summing the time required to complete the hardware instructions within the loop; and
multiplying the time required to complete the hardware instructions within a loop by the number of iterations of the loop.
29. The method of claim 26 , wherein the act of identifying loops comprises reading loop directive identifiers in the source code.