Patent Assignment
Reel/Frame 056702/0387
Merger and Change of Name
Recorded: 2021-06-29
Pages: 7
Assignors
MENTOR GRAPHICS CORPORATION
Executed: 2020-12-30
SIEMENS INDUSTRY SOFTWARE INC.
Executed: 2020-12-30
Assignee
SIEMENS INDUSTRY SOFTWARE INC.
5800 GRANITE PARKWAY, SUITE 600, PLANO, TEXAS, 75024
Covered Properties
(94)
Synchronization Point Across Different Memory Bist Controllers
Patent:
7,036,064 →
Application:
09/872,212 →
Graphical Loop Profile Analysis
Self-Describing Ip Package for Enhanced Platform Based Soc Design
Digital Circuit Layout Techniques Using Identification of Input Equivalence
Method for Synthesizing Linear Finite State Machines
Test Pattern Compression for an Integrated Circuit Test Environment
Distributed Autorouting of Conductive Paths in Printed Circuit Boards
System Verification Using One or More Automata
Method and Apparatus for Selectively Compacting Test Responses
Integrated Opc Verification Tool
Adaptive Fault Diagnosis of Compressed Test Responses
Determining and Analyzing Integrated Circuit Yield and Quality
Programmable Memory Built-in-Self-Test (Mbist) Method and Apparatus
Decompressor/Prpg for Applying Pseudo-Random and Deterministic Test Patterns
Direct Fault Diagnostics Using Per-Pattern Compactor Signatures
Contrast Based Resolution Enhancement for Photolithographic Processing
Conversion of Circuit Description to a Transaction Model
Structured Algorithmic Programming Language Approach to System Design
Decompressors for Low Power Decompression of Test Patterns
Phase Shifter with Reduced Linear Dependency
Use of Breakouts in Printed Circuit Board Designs
Interactive Interface Resource Allocation in a Behavioral Synthesis Tool
Dram with Reduced Power Consumption
Metastability Effects Simulation for a Circuit Description
Loop Manipulation If a Behavioral Synthesis Tool
Offset Fill
Hybrid Dram
Synthesis Strategies Based on the Appropriate Use of Inductance Effects
Multi-Port Sram Implemented with Single-Port 6-Transistor Memory Cells Coupled to an Input Multiplexer and an Output Demultiplexer
Leakage Control
Continuous Application and Decompression of Test Patterns to a Circuit-Under-Test
Mutual Inductance Extraction Using Dipole Approximations
High-Frequency Vlsi Interconnect and Intentional Inductor Impedance Extraction in the Presence of a Multi-Layer Conductive Substrate
Source Optimization by Assigning Pixel Intensities for Diffractive Optical Element Using Mathematical Relationship
Decompressors for Low Power Decompression of Test Patterns
Mask Decomposition for Double Dipole Lithography
Test Generation Methods for Reducing Power Dissipation and Supply Currents
Model-Based Fill
Extracting High Frequency Impedance in a Circuit Design Using an Electronic Design Automation Tool
Hierarchical Feature Extraction for Electrical Interaction Calculations
Testing Embedded Memories in an Integrated Circuit
Sum of Coherent Systems (Socs) Approximation Based on Object Information
Logic-Driven Layout Verification
Methods for at-Speed Testing of Memory Interface
Measure of Analysis Performed in Property Checking
Low Power Scan Testing Techniques and Apparatus
Thermal Analysis
Contour Alignment for Model Calibration
Modeling the Skin Effect Using Efficient Conduction Mode Techniques
Inverse Mask Design and Correction for Electronic Design
Analysis Optimzer
Selective Per-Cycle Masking of Scan Chains for System Level Test
Generating Test Sets for Diagnosing Scan Chain Failures
Trace Routing Network
Fault Diagnosis Based on Design Partitioning
Logic Injection
Random Access Memory for Use in an Emulation Environment
Data Flow Branching in Mask Data Preparation
Test Pattern Generation for Diagnosing Scan Chain Failures
Diagnosis-Aware Scan Chain Stitching
Input Space Reduction for Verification Test Set Generation
Designing Wiring Harnesses
Third Party Component Debugging for Integrated Circuit Design
Generating Transmission-Code Compliant Test Sequences
Scan Chain Configuration For Test-Per-Clock Based On Circuit Topology
Fault Support in an Emulation Environment
Test Access Architecture For Stacked Dies
Patent:
9,389,945 →
Application:
14/022,216 →
Timing-Aware Test Generation and Fault Simulation
Dynamic Printed Circuit Board Design Reuse
Resource Mapping in a Hardware Emulation Environment
Managing and Controlling the Use of Hardware Resources on Integrated Circuits
Method and Circuit Of Pulse-Vanishing Test
Hierarchical Verification of Clock Domain Crossings
Layout Decomposition For Multiple Patterning Lithography
Patent:
9,679,095 →
Application:
14/493,089 →
Coherent State Among Multiple Simulation Models In An EDA Simulation Environment
Tag Based System For Leveraging Design Data
Application:
14/610,725 →
Publication:
US 2015/0213069
System Design Management
Hardware Simulation Controller, System and Method for Functional Verification
Formal Verification Using Microtransactions
Patent:
9,817,929 →
Application:
14/664,763 →
Verification Of Photonic Integrated Circuits
Expanded Canonical Forms Of Layout Patterns
Clock Tree Synthesis Graphical User Interface
Tolerant of Absolute Offsets Physical Unclonable Function Device
Testbench Restoration Based on Capture and Replay
Design and Manufacture of Non-Rectilinear Features
Mask Creation with Hierarchy Management Using Cover Cells
Dynamic Design Partitioning for Diagnosis
Integrated Circuit Layout Design Methodology with Process Variation Bands
Statistical Channel Analysis with Correlated Multiple-Level Input Modulation
Generating Root Cause Candidates for Yield Analysis
Event Queue Management for Embedded Systems
Debug Environment for a Multi User Hardware Assisted Verification System
Application:
15/646,003 →
Publication:
US 2018/0032357
Traffic Shaping In Networking System-On-Chip Verification
Data Generation For Streaming Networks In Circuits
Patent:
10,476,740 →
Application:
15/925,649 →
Related Assignments
(20)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Oct 17, 2001
From: KEBICHI, OMAR; CHENG, WU-TUNG; HILL, CHRISTOPHER JOHN; REUTER, PAUL J.
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 012282/0020 →
Assignment of Assignor's Interest
Jun 18, 2004
From: PETUNIN, VLADIMIR V.; PFEIL, CHARLES L.; NATARAJAN, VENKAT; SMITH, EDWIN FRANKLIN
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 015493/0191 →
Assignment of Assignor's Interest
Aug 18, 2004
From: STARKOV, ALEXANDER N.; HYPERGRAPH
To: MENTOR GRAPHICS
Reel/Frame 015690/0790 →
Assignment of Assignor's Interest
Sep 30, 2004
From: KADKADE, SUDHIR DATTARAM; LYONS, JR., CLIFTON ALTON
To: LIGHTHOUSE DESIGN AUTOMATION, INC.
Reel/Frame 015873/0163 →
Assignment of Assignor's Interest
Oct 25, 2004
From: RAJSKI, JANUSZ; TYSZER, JERZY; KASSAB, MARK; MUKHERJEE, NILANJAN
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 015938/0979 →
Assignment of Assignor's Interest
Aug 22, 2005
From: COBB, NICOLAS B.; MILOSLAVSKY, EUGENE
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 016919/0400 →
Retroactive Assignment and Quitclaim
Sep 20, 2005
From: MENTOR GRAPHICS (UK) LIMITED; SHROSPHIRE, ARTHUR EDWARD; CHEN, MICHAEL Y.; BROUHARD, MICHAEL C.
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 016547/0974 →
Assignment of Assignor's Interest
Oct 24, 2005
From: RAJSKI, JANUSZ; CHEN, GANG; KEIM, MARTIN; TAMARAPALLI, NAGESH
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 016675/0106 →
Assignment of Assignor's Interest
Nov 22, 2005
From: RAJSKI, JANUSZ; MRUGALSKI, GRZEGORZ; POGIEL, ARTUR; TYSZER, JERZY
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 016809/0189 →
Assignment of Assignor's Interest
Feb 13, 2006
From: MUKHERJEE, NILANJAN; DU, XIAOGANG; CHENG, WU-TUNG
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 017256/0924 →
Assignment of Assignor's Interest
Jul 13, 2006
From: LIGHTHOUSE DESIGN AUTOMATION, INC.
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 017928/0425 →
Assignment of Assignor's Interest
Oct 12, 2006
From: RAJSKI, JANUSZ; TYSZER, JERZY; KASSAB, MARK; MUKHERJEE, NILANJAN
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 018382/0816 →
Merger
Oct 25, 2006
From: EXEMPLAR LOGIC, INC.
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 018449/0910 →
Assignment of Assignor's Interest
Oct 25, 2006
From: WALLACE, DAVID E.
To: EXEMPLAR LOGIC, INC.
Reel/Frame 018449/0800 →
Assignment of Assignor's Interest
Jan 10, 2007
From: CHENG, WU-TUNG; SHARMA, MANISH; RINDERKNECHT, THOMAS HANS
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 018741/0214 →
Assignment of Assignor's Interest
Jul 31, 2007
From: VELLER, YOSSI; HANGA, VASILE; ROZENMAN, ALEXANDER; RACHAMIM, RAMI
To: MENTOR GRAPHICS (ISRAEL) LIMITED
Reel/Frame 019626/0946 →
Assignment of Assignor's Interest
May 28, 2008
From: TORRES ROBLES, JUAN ANDRES; GRANIK, YURI
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 021011/0682 →
Assignment of Assignor's Interest
Nov 30, 2009
From: NORTHROP GRUMMAN CORPORTION
To: NORTHROP GRUMMAN SPACE & MISSION SYSTEMS CORP.
Reel/Frame 023699/0551 →
Assignment of Assignor's Interest
Dec 17, 2009
From: MENTOR GRAPHICS (ISRAEL) LIMITED
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 023667/0042 →
Assignment of Assignor's Interest
Feb 10, 2010
From: NORTHROP GRUMMAN SPACE & MISSION SYSTEMS CORP.
To: NORTHROP GRUMMAN SYSTEMS CORPORATION
Reel/Frame 023915/0446 →