Leakage control
View Patent ↗In one embodiment, a leakage reduction circuit is provided that includes: a virtual power supply node; a first PMOS transistor coupled between the virtual power supply node and a power supply node; a second PMOS transistor having a source coupled to the power supply node; and a native NMOS transistor coupled between a drain of the second PMOS transistor and the virtual power supply node, the native NMOS transistor having a gate driven by the power supply node.
1. A leakage reduction circuit, comprising:
a virtual power supply node;
a first PMOS transistor coupled between the virtual power supply node and a power supply node;
a second PMOS transistor having a source coupled to the power supply node; and
a native NMOS transistor coupled between a drain of the second PMOS transistor and the virtual power supply node, the native NMOS transistor having a gate driven by the power supply node.
2. The leakage reduction circuit of claim 1 , further comprising at least one leaking transistor powered by the virtual power supply node, wherein a gate for the first PMOS transistor is controlled by a normal mode signal asserted during normal mode operation of the at least one leaking transistor.
3. The leakage reduction circuit of claim 2 , wherein a gate of the second PMOS transistor is controlled by a standby mode signal asserted during standby mode operation of the at least one leaking transistor.
4. The leakage reduction circuit of claim 3 , wherein the at least one leaking transistor comprises a CMOS inverter.