Method and circuit of pulse-vanishing test
View Patent ↗Various aspects of the disclose techniques relate to techniques of testing interconnects in stacked designs. A single-pulse signal, generated by a first circuit state element on a first die, is applied to a first end of an interconnect and captured at a second end of the interconnect using a clock port of a second circuit state element on a second die. A faulty interconnect may cause the single-pulse signal too distorted to reach the threshold voltage of the second circuit element.
1. A method, comprising:
applying a single-pulse signal, generated by a first circuit state element on a first die, to a first end of an interconnect; and
capturing, through a clock port of a second circuit state element on a second die, the single-pulse signal at a second end of the interconnect, wherein during the applying and the capturing, a constant signal of one logic value is applied to an input port of the second circuit state element, the one logic value being opposite to a logic value stored in the second circuit state element before the capturing.
2. The method recited in claim 1 , wherein the first circuit state element, the second circuit state element or both are flip-flops.
3. The method recited in claim 1 , wherein the interconnect is an interposer wire and the first die and the second die are two-and-half-dimensional stacked integrated circuits.
4. The method recited in claim 1 , wherein the first circuit state element is comprised by a boundary scan cell on the first die and the second circuit state element is comprised by a boundary scan cell on the second die.
5. The method recited in claim 1 , wherein the single-pulse signal is generated by applying a double-pulse signal to a clock port of the first circuit state element.
6. An integrated circuit, comprising:
a first die comprising a first circuit state element configurable to generate a single-pulse signal;
a second die comprising a second circuit state element configurable to capture the single-pulse signal through a clock port of the second circuit state element, wherein during the generation of the single-pulse signal and the capture of the single-pulse signal, a constant signal of one logical value is applied to an input port of the second circuit state element, the one logic value being opposite to a logical value stored in the second circuit state element before the capture; and
an interconnect through which the single-pulse signal travels from the first die to the second die.
7. The integrated circuit recited in claim 6 , wherein the interconnect is an interposer wire and the first die and the second die are two-and-half-dimensional stacked integrated circuits.
8. The integrated circuit recited in claim 6 , wherein the first circuit state element, the second circuit state element or both are flip-flops.
9. The integrated circuit recited in claim 6 , wherein the first circuit state element is comprised by a boundary scan cell on the first die and the second circuit state element is comprised by a boundary scan cell on the second die.
10. The integrated circuit recited in claim 6 , wherein the single-pulse signal is generated by applying a double-pulse signal to a clock port of the first circuit state element.