Coherent state among multiple simulation models in an EDA simulation environment
View Patent ↗A circuit design is simulated in a simulation environment. When a simulation model in the simulation environment transfers state information to a second simulation model, the simulation environment receives the state information and makes it available to the second simulation model without simulating the transfer through the simulated circuit design.
1. A method comprising:
receiving a circuit design having at least a hardware component and a software component in a simulation environment;
simulating at least part of the software component using a software simulator;
simulating at least part of the hardware component using a hardware simulator, the hardware simulator including a plurality of field programmable gate arrays (FPGAs) to simulate the hardware component, wherein at least a portion of the simulation by the software simulator is performed at the same time as the simulation by the hardware simulator; and
selectively activating and deactivating particular simulation domains in the simulation environment such that a resolution and a performance for the circuit design being simulated is dynamically modified.
2. The method of claim 1 wherein said simulation environment comprises a plurality of simulation domains, the plurality of simulation domains including the software simulator, a logic simulator and a programming language simulator, where each simulation domain contains at least one simulation model, each of the software simulator, logic simulator and programming language simulator being connected to a bus model that includes a detailed pin-level model of a bus;
wherein the pin-level model of the bus is bypassed by using a protocol engine of the bus model to directly access a coherent memory.
3. The method of claim 1 , wherein the simulation domains have access to state information using a coherent state storage to transfer state information among the simulation domains.
4. The method of claim 1 further including transferring state information between the simulation domains without simulating the transfers.
5. The method of claim 1 , further including partitioning the circuit design into the simulation domains based on a partition criteria.
6. The method of claim 5 , wherein the partition criteria comprises at least one of an abstraction level, a simulation type, and a function type.
7. The method of claim 1 , wherein the simulation domains operate at the same time but at different operating frequencies.
8. The method of claim 1 , further including passing a transaction to the simulation environment with information related to the selected activation and deactivation of the simulation domains.
9. A system comprising:
means for receiving a circuit design having at least a hardware component and a software component in a simulation environment;
a software simulator configured to simulate at least part of the software component;
a hardware simulator configured to simulate at least part of the hardware component, the hardware simulator including a plurality of field programmable gate arrays (FPGAs) to simulate the hardware component, wherein at least a portion of the simulation by the software simulator is performed at the same time as the simulation by the hardware simulator; and
means for selectively activating and deactivating particular simulation domains in the simulation environment such that a resolution and a performance for the circuit design being simulated is dynamically modified.
10. The system of claim 9 wherein said simulation environment comprises a plurality of simulation domains, the plurality of simulation domains including the software simulator, a logic simulator and a programming language simulator, where each simulation domain contains at least one simulation model, each of the software simulator, logic simulator and programming language simulator being connected to a bus model that includes a detailed pin-level model of a bus;
wherein the pin-level model of the bus is bypassed by using a protocol engine of the bus model to directly access a coherent memory.
11. The system of claim 9 , wherein the simulation domains have access to state information using a coherent state storage to transfer state information among the simulation domains.
12. The system of claim 9 further including means for transferring state information between the simulation domains without simulating the transfers.
13. The system of claim 9 , further including means for partitioning the circuit design into the simulation domains based on a partition criteria.
14. The system of claim 13 , wherein the partition criteria comprises at least one of an abstraction level, a simulation type, and a function type.
15. The system of claim 9 , wherein the simulation domains operate at the same time but at different operating frequencies.
16. The system of claim 9 , further including means for passing a transaction to the simulation environment with information related to the selected activation and deactivation of the simulation domains.