Multi-port SRAM implemented with single-port 6-transistor memory cells coupled to an input multiplexer and an output demultiplexer

1. A multi-port 6-Transistor (6-T) SRAM, comprising:

a single input port and output port 6-T SRAM; and

a multi-port control block circuit that includes:

a plurality of input registers corresponding to a plurality of input ports to register corresponding input signals;

an input multiplexer coupled to the input registers to provide a selected input signal to the 6-T SRAM's single input port;

a plurality of output registers corresponding to a plurality of output ports to register corresponding output signals; and

an output de-multiplexer coupled to the output registers to provide an output signal from the 6-T SRAM's single output port to the selected output register.

2. The multi-port 6-T SRAM of claim 1 , wherein the 6-T SRAM is configured to initiate a read or write cycle responsive to the assertion of an internal clock and includes a delay circuit configured to assert a finish signal upon the completion of the read or write cycle.

3. The multi-port 6-T SRAM of claim 2 , wherein the control block circuit includes a logic circuit configured to initiate the read or write cycle responsive to the assertion of the external clock.

4. The multi-port 6-T SRAM of claim 3 , wherein the logic circuit is further configured to control the input multiplexer to sequentially select from the input registers during the write cycle and to control the output de-multiplexer to sequentially select from the output registers during the read cycle.

5. The multi-port 6-T SRAM of claim 3 , wherein the logic circuit is further configured to control the input multiplexer to non-sequentially select from the input registers during the write cycle and to control the output de-multiplexer to non-sequentially select from the output registers during the read cycle.

6. The multi-port 6-T SRAM of claim 3 , wherein the logic circuit is configured to de-assert the internal clock responsive to an assertion of the finish signal.

7. A method of writing to a single-port 6-T SRAM through a multi-port control circuit, the multi-port control circuit including a plurality n of input ports; comprising:

asserting an external clock indicating the beginning of a write cycle while receiving a plurality n of input in parallel at the plurality of input ports;

storing the plurality of input words in a storage responsive to the assertion of the external clock;

selecting a first input word from the storage to provide the first input word to the SRAM while asserting an internal clock to the SRAM to initiate an internal write cycle in the SRAM;

asserting a finish signal indicating that the internal write cycle is completed;

de-asserting the internal clock responsive to the assertion of the finish signal; and

de-asserting the finish signal responsive to the de-assertion of the internal clock.

8. The method of claim 7 , further comprising:

selecting a subsequent input word from the storage to provide the subsequent input word to the SRAM while re-asserting the internal clock to initiate an additional internal write cycle in the SRAM;

re-asserting the finish signal indicating that the additional internal write cycle is completed;

de-asserting the internal clock responsive to the re-assertion of the finish signal; and

de-asserting the finish signal responsive to the de-assertion of the internal clock.

9. The method of claim 8 , comprising:

continuing to initiate additional internal write cycles until all n input words are written to the SRAM, wherein the finish signal is asserted after completion of each internal write cycle.

10. The method of claim 8 , wherein the selection of the input words from the storage occurs through a multiplexer.

11. The method of claim 8 , wherein the storage comprises a plurality of registers.

12. The method of claim 8 , wherein the storage comprises a plurality of latches.

13. The method of claim 8 , wherein the storage comprises a buffer.

14. A method of reading from a single-port 6-T SRAM through a multi-port control circuit, the multi-port control circuit including a plurality n of output ports; comprising:

asserting an external clock indicating the beginning of a read cycle;

asserting an internal clock to the SRAM responsive to the assertion of the external clock to initiate a first internal read cycle to read a first output word;

asserting a finish signal upon the completion of the first internal read cycle;

demultiplexing the first output word to a first one of a plurality of n registers responsive to the assertion of the finish signal;

de-asserting the internal clock responsive to the assertion of the finish signal; and

de-asserting the finish signal responsive to the de-assertion of the internal clock.

15. The method of claim 14 , further comprising:

re-asserting the internal clock to the SRAM to initiate a second internal read cycle to read a second output word;

re-asserting the finish signal upon the completion of the second internal read cycle;

demultiplexing the second output word to .a second one of the plurality of n registers responsive to the re-assertion of the finish signal;

de-asserting the internal clock responsive to the re-assertion of the finish signal; and

de-asserting the finish signal responsive to the de-assertion of the internal clock.

16. The method of claim 15 , further comprising:

continuing to initiate additional internal read cycles until all n output words are written to the n registers, wherein the finish signal is asserted after completion of each internal read cycle.