Loop manipulation if a behavioral synthesis tool

1. A computer-readable storage having stored thereon computer-executable instructions to perform a method in a behavioral synthesis tool used to design a hardware circuit, a method comprising:

loading into the behavioral synthesis tool, source code associated with the hardware circuit;

in the source code, identifying a subset of variables from an array including a multi-variable memory space that are accessed by a plurality of loops;

merging at least two of the plurality of loops into a single merged loop;

storing the subset of variables in a separately accessible memory space that includes a shift register or a cyclic buffer; and

accessing one of the stored subset of variables to recover a stored value of the one of the stored subset of variables for use by at least one of the plurality of loops during synthesis.

2. The method of claim 1 , wherein identifying a subset of variables comprises determining that a plurality of memory accesses from inside one of the plurality of loops comprises linear loop expressions.

3. The method of claim 2 , wherein identifying a subset of variables further comprises determining that a plurality of memory accesses from outside the one of the plurality of loops comprises constant indexes.

4. The behavioral synthesis tool of claim 1 , further including transforming the array to the shift register or cyclic buffer.

5. The behavioral synthesis tool of claim 4 , wherein array accesses before the plurality of loops are directly transformed to the shift register or cyclic buffer.

6. The behavioral synthesis tool of claim 4 , wherein array accesses after the plurality of loops take into account how often at least one of the subset of variables is incremented.

7. A computer-readable storage having stored thereon computer-executable instructions for performing a method of designing an integrated circuit, the method comprising:

loading into a behavioral synthesis tool, source code associated with the integrated circuit;

identifying at least a first loop and a second loop in the source code;

determining whether a dependency exists between the first loop and the second loop;

identifying at least one array designation inside the first or second loop; and

merging the first loop and the second loop into a single merged loop, wherein the merging comprises mapping a plurality of memory accesses from the first loop to a sliding window, wherein the sliding window including transforming the array designation into a shift register or a cyclic buffer.

8. The method of claim 7 , wherein the merging further comprises mapping a plurality of memory accesses from the second loop to the sliding window.

9. The method of claim 7 , wherein the plurality of memory accesses from the first loop comprises a plurality of accesses to non-sequential memory locations.

10. The behavioral synthesis tool of claim 7 , wherein array accesses before the plurality of loops are directly transformed to the shift register or cyclic buffer.

11. The behavioral synthesis tool of claim 7 , wherein array accesses after the plurality of loops take into account how often at least one of the subset of variables is incremented.

12. A computer-readable storage having stored thereon computer-executable instructions for executing a method of designing an integrated circuit, the method comprising:

loading into a behavioral synthesis tool, source code associated with the integrated circuit;

identifying at least a first loop and a second loop in the source code;

identifying at least one array designation inside the first or second loop; and

merging the first loop and the second loop into a single merged loop, wherein the merging includes transforming the array designation into a shift register in the behavioral synthesis tool's representation of the integrated circuit.

13. The behavioral synthesis tool of claim 12 , wherein array accesses before the first and second loops are directly transformed to the shift register or cyclic buffer.

14. The behavioral synthesis tool of claim 12 , wherein array accesses after the first and second loops take into account how often a loop variable is incremented.