Test pattern compression for an integrated circuit test environment

1. A method that computes a compressed test pattern to test an integrated circuit, comprising:

(a) generating a preliminary set of equations associated with the compressed test pattern;

(b) attempting to solve the set of equations;

(c) if the attempt to solve the equations fails, deleting a most recently appended equation; and

(d) if the attempt to solve the equations is successful, incrementally appending additional equations onto the set of equations;

(e) repeating (b), (c) and (d) to generate a final set of equations;

(f) solving the final set of equations to obtain the compressed test pattern.

2. The method of claim 1 , wherein the repeating occurs until a predetermined limiting criteria is reached.

3. The method of claim 1 , further including generating symbolic expressions associated with scan cells within the integrated circuit, the symbolic expressions associated with input variables applied concurrently while the scan cells are being loaded.

4. The method of claim 1 , further including storing the compressed test pattern in an ATE and transferring the compressed test pattern to an integrated circuit being tested, wherein the integrated circuit includes a decompressor.

5. The method of claim 1 , further including generating symbolic expressions including:

assigning input variables to bits on input channels to the integrated circuit, wherein the number of input variables is larger than the number of channels;

simulating the application of the input variables to a decompressor in the integrated circuit and simulating that the decompressor is continually clocked to decompress the input variables, wherein one or more additional input variables are injected into the decompressor during one or more clock cycles; and

generating a set of output expressions from the decompressor that results from the simulation, wherein the output expressions are based on the input variables that are injected as the decompressor is continually clocked.

6. The method of claim 5 , further including assigning each of the output expressions to each scan cell within a scan chain in the integrated circuit.

7. The method of claim 1 , wherein solving the equations includes performing a Gauss-Jordon elimination method for solving equations.

8. The method of claim 1 , further including generating a test cube including assigning values of a predetermined logic 1 or a predetermined logic 0 to scan cells for testing a fault in the integrated circuit.

9. The method of claim 1 , further including:

(a) applying the compressed test pattern to the integrated circuit;

(b) decompressing the test pattern; and

(c) loading scan cells within the integrated circuit with the decompressed test pattern;

(d) wherein (a), (b) and (c) occur substantially concurrently.

10. The method of claim 1 , wherein generating the final set of equations includes:

associating symbolic expressions in a one-to-one relationship with a scan cell; and

for each scan cell having a predetermined assigned value, equating the symbolic expression associated with that scan cell to the predetermined assigned value.

11. The method of claim 1 , further including generating symbolic expressions that are associated with scan cells in the integrated circuit, wherein generating symbolic expressions includes using a mathematical representation of a decompressor.

12. A method that computes a compressed test pattern to test an integrated circuit, comprising:

using simulation, generating symbolic expressions that are associated with simulated scan cells of an integrated circuit;

generating a test cube having the scan cells assigned predetermined values; and

formulating a set of equations by equating the assigned values in the scan cells to the symbolic expressions; and

determine if the equations are solvable, and if not, remove the last equation.

13. The method of claim 12 , wherein, if the equations are solvable, appending an equation onto the test cube.

14. The method of claim 13 , further including repeatedly deleting the recently appended equations until a limiting criteria is met or exceeded.

15. The method of claim 12 , further including solving the equations by performing a Gauss-Jordon elimination method for solving equations to generate a compressed test pattern.

16. The method of claim 15 , further including storing the compressed test pattern in an ATE and transferring the compressed test pattern to an integrated circuit being tested, wherein the integrated circuit includes a decompressor.

17. The method of claim 15 , further including:

(a) applying the compressed test pattern to the integrated circuit;

(b) decompressing the test pattern; and

(c) loading scan cells within the integrated circuit with the decompressed test pattern;

(d) wherein (a), (b) and (c) occur substantially concurrently.

18. The method of claim 12 , further including generating symbolic expressions, which includes:

assigning input variables to bits on input channels to the integrated circuit, wherein the number of input variables is larger than the number of channels;

simulating the application of the input variables to a decompressor in the integrated circuit and simulating that the decompressor is continually clocked to decompress the input variables, wherein one or more additional input variables are injected into the decompressor during one or more clock cycles; and

generating a set of output expressions from the decompressor that results from the simulation, wherein the output expressions are based on the input variables that are injected as the decompressor is continually clocked.

19. The method of claim 12 , wherein generating a test cube includes assigning values of a predetermined logic 1 or a predetermined logic 0 to the scan cells for testing a fault in the integrated circuit.