Timing-aware test generation and fault simulation
View Patent ↗Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.
1. A method of generating test patterns for testing an integrated circuit, comprising:
identifying a fault that is detected by a test pattern by simulating a response of an integrated circuit design to the test pattern in the presence of the fault and identifying one or more paths that are sensitized by the test pattern and that detect the fault;
determining that the identified fault is to be removed from a fault list, the determination being based at least in part on a relative difference between actual slack and static slack of the shortest sensitized path detecting the identified fault, wherein the actual slack is determined by actual path delay through the shortest sensitized path detecting the fault and the static slack is determined by static path delay through the shortest sensitized path detecting the fault;
modifying the fault list by removing the identified fault; and
storing the modified fault list.
2. The method of claim 1 , wherein the act of determining comprises determining whether the difference satisfies a user-selected criteria.
3. The method of claim 1 , wherein the method is repeated for additional faults in the fault list not detected by previously generated test patterns.
4. The method of claim 1 , wherein the act of identifying further comprises:
performing a good machine simulation to determine a response of the integrated circuit design to the test pattern in the absence of any faults; and
identifying one or more paths sensitized by the test pattern.
5. A method of generating test patterns for testing an integrated circuit, comprising:
identifying a fault that is detected by a test pattern by simulating a response of an integrated circuit design to the test pattern in the presence of the fault and identifying one or more paths that are sensitized by the test pattern and that detect the fault;
determining that the identified fault is to be removed from a fault list;
modifying the fault list by removing the identified fault; and
storing the modified fault list,
wherein the act of determining comprises determining that the following condition is met:
PD
f
s
-
PD
f
a
T
TC
-
PD
f
a
<
δ
,
where PD f s is static path delay for the fault f, PD f a is actual path delay for the fault, T TC is a test clock period, and δ is a real number between 0 and 1.
6. The method of claim 5 , wherein δ is user-selectable.
7. A method of generating test patterns for testing an integrated circuit, comprising:
identifying a fault that is detected by a test pattern by simulating a response of an integrated circuit design to the test pattern in the presence of the fault and identifying one or more paths that are sensitized by the test pattern and that detect the fault;
determining that the identified fault is to be removed from a fault list;
modifying the fault list by removing the identified fault; and
storing the modified fault list,
wherein the act of determining comprises determining that the following condition is met:
HPD
f
a
-
HPD
f
s
T
TC
-
HPD
f
s
<
δ
,
where HPD f s is static path delay through the shortest sensitized path for the fault f, HPD f a is actual path delay through the shortest sensitized path for the fault, T TC is a test clock period, and δ is a real number between 0 and 1.
8. The method of claim 7 , wherein δ is user-selectable.
9. One or more non-transitory computer-readable media storing computer-executable instructions for causing a computer to perform a method of generating test patterns for testing an integrated circuit, comprising:
identifying a fault that is detected by a test pattern by simulating a response of an integrated circuit design to the test pattern in the presence of the fault and identifying one or more paths that are sensitized by the test pattern and that detect the fault;
determining that the identified fault is to be removed from a fault list, the determination being based at least in part on a relative difference between actual slack and static slack of the shortest sensitized path detecting the identified fault, wherein the actual slack is determined by actual path delay through the shortest sensitized path detecting the fault and the static slack is determined by static path delay through the shortest sensitized path detecting the fault;
modifying the fault list by removing the identified fault; and
storing the modified fault list.
10. The one or more non-transitory computer-readable media of claim 9 , wherein the act of determining comprises determining whether the difference satisfies a user-selected criteria.
11. The one or more non-transitory computer-readable media of claim 9 , wherein the act of identifying further comprises:
performing a good machine simulation to determine a response of the integrated circuit design to the test pattern in the absence of any faults; and
identifying one or more paths sensitized by the test pattern.
12. One or more non-transitory computer-readable media storing computer-executable instructions for causing a computer to perform a method of generating test patterns for testing an integrated circuit, comprising:
identifying a fault that is detected by a test pattern by simulating a response of an integrated circuit design to the test pattern in the presence of the fault and identifying one or more paths that are sensitized by the test pattern and that detect the fault;
determining that the identified fault is to be removed from a fault list;
modifying the fault list by removing the identified fault; and
storing the modified fault list,
wherein the act of determining comprises determining that the following condition is met:
PD
f
s
-
PD
f
a
T
TC
-
PD
f
a
<
δ
,
where PD f s is static path delay for the fault f, PD f a is actual path delay for the fault, T TC is a test clock period, and δ is a real number between 0 and 1.
13. One or more non-transitory computer-readable media storing computer-executable instructions for causing a computer to perform a method of generating test patterns for testing an integrated circuit, comprising:
identifying a fault that is detected by a test pattern by simulating a response of an integrated circuit design to the test pattern in the presence of the fault and identifying one or more paths that are sensitized by the test pattern and that detect the fault;
determining that the identified fault is to be removed from a fault list;
modifying the fault list by removing the identified fault; and
storing the modified fault list,
wherein the act of determining comprises determining that the following condition is met:
HPD
f
a
-
HPD
f
s
T
TC
-
HPD
f
s
<
δ
,
where HPD f s is static path delay through the shortest sensitized path for the fault f, HPD f a is actual path delay through the shortest sensitized path for the fault, T TC is a test clock period, and δ is a real number between 0 and 1.