Clock tree synthesis graphical user interface
View Patent ↗In one embodiment, a method for performing an analysis of a synthesized clock tree can include: displaying a plurality of variation parameters and one or more analysis values on a display screen; accepting a first signal from a user input device to select one of the variation parameters; accepting a second signal from a user input device to select one or more of the analysis values; and displaying a plurality of pins from the synthesized clock tree with the selected variation parameter and the selected one or more analysis values on the display screen.
1. A method for managing a volume of data, pertaining to a synthesized clock tree, on a graphical user interface (GUI), the method comprising:
displaying, on a display screen, a plurality of variation parameters for the synthesized clock tree, wherein the synthesized clock tree includes a plurality of pins, and one or more timing analysis result values associated with at least one of the plurality of pins, the variation parameters comprising one or more of process variations, voltage variations, temperature variations, or library model variations;
accepting a first signal from a user input device to select one of the variation parameters;
accepting a second signal from the user input device to select one or more of the timing analysis result values; and
displaying, on the display screen, at least one of the plurality of pins from the synthesized clock tree with the selected process variation parameter and the selected one or more timing analysis result values.
2. The method of claim 1 , further comprising:
accepting a third signal from the user input device for selecting one of the plurality of pins; and
displaying on the display screen a layout path trace corresponding to the selected pin.
3. The method of claim 1 , wherein the displaying the plurality of pins comprises displaying a bar chart plot.
4. The method of claim 1 , wherein the displaying the plurality of pins comprises displaying an XY graph plot.
5. The method of claim 1 , wherein the plurality of variation parameters comprises process, voltage, temperature, and library model variations.
6. The method of claim 1 , wherein the one or more timing analysis result values comprise one or more of the following: rise latency, rise skew, fall latency, fall skew, rise slew minimum, or fall slew minimum.
7. The method of claim 1 , wherein the one or more timing analysis result values comprise capacitance.
8. An apparatus, comprising:
one or more processors; and
logic encoded in one or more tangible media for execution by the one or more processors, that when executed by the one or more processors causes the processors to perform a method for managing a volume of data, pertaining to a synthesized clock tree, on a graphical user interface (GUI), the method comprising:
displaying a plurality of variation parameters for the synthesized clock tree, wherein the synthesized clock tree includes a plurality of pins, and one or more timing analysis result values associated with at least one of the plurality of pins, the variation parameters comprising one or more of process variations, voltage variations, temperature variations, or library model variations;
accepting a first signal from a first user input device to select one of the variation parameters;
accepting a second signal from a second user input device to select one or more of the timing analysis result values; and
displaying at least one of the plurality of pins from the synthesized clock tree with the selected variation parameter and the selected one or more timing analysis result values on a display screen.
9. The apparatus of claim 8 , wherein the method further comprises:
accepting a third signal from a third user input device for selecting one of the plurality of pins; and
displaying a layout path trace corresponding to the selected pin.
10. The apparatus of claim 8 , wherein:
the displaying comprises displaying a plot; and
the plurality of variation parameters comprises process, voltage, temperature, and library model variations.
11. The apparatus of claim 8 , wherein the one or more timing analysis result values comprise capacitance.
12. The apparatus of claim 8 , wherein the one or more timing analysis result values comprise one or more of the following: latency, skew, or slew.
13. A tangible computer-readable storage device including instructions executable by a processor, that when executed by the processor cause the processor to perform a method for managing a volume of data, pertaining to a synthesized clock tree, on a graphical user interface (GUI), the method comprising:
displaying a plurality of variation parameters for the synthesized clock tree, wherein the synthesized clock tree includes a plurality of pins, and one or more timing analysis result values associated with at least one of the plurality of pins, the variation parameters comprising one or more of process variations, voltage variations, temperature variations, or library model variations;
accepting a first signal from a user input device to select one of the variation parameters;
accepting a second signal from the user input device to select one or more of the timing analysis result values; and
displaying at least one of the plurality of pins from the synthesized clock tree with the selected variation parameter and the selected one or more timing analysis result values.
14. The computer-readable storage device of claim 13 , wherein the method further comprises:
accepting a third signal from the user input device for selecting one of the plurality of pins; and
displaying on the display screen a layout path trace corresponding to the selected pin.
15. The computer-readable storage device of claim 13 , wherein the plurality of variation parameters comprises process, voltage, and temperature variations.
16. The computer-readable storage device of claim 13 , wherein the one or more timing analysis result values comprise one or more of the following: rise latency, rise skew, fall latency, fall skew, rise slew minimum, and fall slew minimum.
17. The computer-readable storage device of claim 13 , wherein the one or more timing analysis result values comprise capacitance.
18. The method of claim 1 , further comprising receiving a design netlist and performing clock tree synthesis for the design netlist.
19. The method of claim 1 , further comprising displaying, on the display screen, a control for selection of corners for two or more of the variation parameters.
20. The method of claim 1 , further comprising displaying, on the display screen, a control for selection of a clock tree node of the synthesized clock tree as a starting point for timing analysis.