IP Library Granted Patent US 10,596,219
Granted Patent B2
US 10,596,219 · App. 13/017,788 · Granted Mar 24, 2020

Logic-driven layout verification

Inventors: Sridhar Srinivasan (Tualatin, OR); Fedor G. Pikus (Beaverton, OR); Patrick D. Gibson (Tualatin, OR); Padmaja Susarla (McLean, VA)
Assignee: Mentor Graphics Corporation
A61K38/00A61K38/4846A61K39/395A61K47/02
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Quick Facts
Patent No.
US 10,596,219
App. No.
13/017,788
Granted
Mar 24, 2020
Kind
B2
Abstract

A check for determining the appropriateness of physical design data is provided, where the check includes both a physical component and a logical component. Based upon the logical component of the check, portions of the physical design data that correspond to the logical component are identified and selected. After the portions of the physical design data corresponding to the logical component have been selected, this physical design data can be provided to a physical design analysis tool, along with the physical component of the design check. The physical design analysis tool can then use the physical component of the design check to perform an analysis of the selected physical design data.

Claims (59)

1. A method comprising:

accessing a circuit design analysis rule that comprises:

a logical component that specifies a specific logical design object; and

a physical component specifying physical analysis criteria to be applied to the specific logical design object;

identifying instances of the specific logical design object in a logical circuit design;

identifying physical structures in layout design data that correspond to the instances of the specific logical design object identified in the logical circuit design;

applying the physical analysis criteria to the physical structures that correspond to each instance of the specific logical design object, wherein the logical circuit design is a source schematic logical circuit design; and

further comprising:

extracting logical design data from the layout design data to obtain an extracted logical circuit design;

correlating logical names in the source schematic logical circuit design to extracted logical design data identifiers that identify portions of the extracted logical circuit design; and

tracking correlations between the logical names in the source schematic logical circuit design to the extracted logical design data identifiers in a cross-reference database.

2. The method of claim 1 , wherein the logical circuit design comprises netlist data; and

wherein identifying instances of the specific logical design object in the logical circuit design comprises:

traversing the netlist data;

identifying elements in the netlist data that correspond to the specific logical design object; and

exporting the identified elements as collections of pin-pairs, nets, devices, or instances.

3. The method of claim 2 , wherein each collection corresponds to a particular instance of the specific logical design object.

4. The method of claim 2 , wherein identifying the physical structures in the layout design data that correspond to the instances of the specific logical design object comprises:

identifying portions of the layout design data corresponding to the identified elements of the netlist data.

5. The method of claim 2 , further comprising extracting the netlist data from the layout design data.

6. The method of claim 1 , wherein identifying the physical structures in the layout design data comprises:

obtaining, from the cross-reference database, particular extracted logical design data identifiers for the portions of the extracted logical circuit design that correspond to the instances of the specific logical design object identified in the source schematic logical circuit design; and

identifying the physical structures from the layout design data that correspond to the particular extracted logical design data identifiers.

7. The method of claim 1 , wherein the physical analysis criteria comprises a design rule check or a design-for-manufacturing check.

8. A non-transitory machine-readable medium comprising instructions that, when executed by a processor, cause a system to:

access a circuit design analysis rule that comprises:

a logical component that specifies a specific logical design object; and

a physical component specifying physical analysis criteria to be applied to the specific logical design object;

identify instances of the specific logical design object in a logical circuit design;

identify physical structures in layout design data that correspond to the instances of the specific logical design object identified in the logical circuit design; and

apply the physical analysis criteria to the physical structures that correspond to each instance of the specific logical design object, wherein the logical circuit design is a source schematic logical circuit design; and

further comprising instructions that, when executed by the processor, cause the system to:

extract logical design data from the layout design data to obtain an extracted logical circuit design;

correlate logical names in the source schematic logical circuit design to extracted logical design data identifiers that identify portions of the extracted logical circuit design; and

track correlations between the logical names in the source schematic logical circuit design to the extracted logical design data identifiers in a cross-reference database.

9. The non-transitory machine-readable medium of claim 8 , wherein the logical circuit design comprises netlist data; and

wherein the instructions to identify instances of the specific logical design object in the logical circuit design comprises instructions that cause the system to:

traverse the netlist data;

identify elements in the netlist data that correspond to the specific logical design object; and

export the identified elements as collections of pin-pairs, nets, devices, or instances.

10. The non-transitory machine-readable medium of claim 9 , wherein each collection corresponds to a particular instance of the specific logical design object.

11. The non-transitory machine-readable medium of claim 9 , wherein the instructions to identify the physical structures in the layout design data that correspond to the instances of the specific logical design object comprise instructions that cause the system to:

identify portions of the layout design data corresponding to the identified elements of the netlist data.

12. The non-transitory machine-readable medium of claim 9 , further comprising instructions that cause the system to extract the netlist data from the layout design data.

13. The non-transitory machine-readable medium of claim 8 , wherein the instructions to identify the physical structures in the layout design data comprise instructions that cause the system to:

obtain, from the cross-reference database, particular extracted logical design data identifiers for the portions of the extracted logical circuit design that correspond to the instances of the specific logical design object identified in the source schematic logical circuit design; and

identify the physical structures from the layout design data that correspond to the particular extracted logical design data identifiers.

14. A system comprising:

a processor; and

a non-transitory machine-readable medium storing instructions that, when executed by the processor, cause the processor to:

access layout design data of a circuit;

extract logical design data from the layout design data;

cross reference the extracted logical design data with logical object names of a schematic netlist and store the cross references in a cross-reference database;

access a circuit design analysis rule that comprises:

a logical component that specifies a specific logical design object using a logical object name from the schematic netlist; and

a physical component specifying physical analysis criteria to be applied to the specific logical design object;

identify instances of the specific logical design object in the schematic netlist;

identify physical structures in the layout design data that correspond to the instances of the specific logical design object identified in schematic netlist using the cross-reference database; and

apply the physical analysis criteria to the physical structures that correspond to each instance of the specific logical design object.

Assignments (2)
MERGER AND CHANGE OF NAME Recorded Jun 29, 2021
From: MENTOR GRAPHICS CORPORATION; SIEMENS INDUSTRY SOFTWARE INC.
To: SIEMENS INDUSTRY SOFTWARE INC.
Reel/Frame 056702/0387 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 23, 2019
From: SRINIVASAN, SRIDHAR; PIKUS, FEDOR G.; GIBSON, PATRICK D.; SUSARLA, PADMAJA
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 048966/0474 →