High-frequency VLSI interconnect and intentional inductor impedance extraction in the presence of a multi-layer conductive substrate
View Patent ↗Embodiments of methods, apparatus, and systems for extracting impedance for a circuit design are disclosed herein. Some of the disclosed embodiments are computationally efficient and can accurately compute the frequency-dependent impedance of VLSI interconnects and/or intentional inductors in the presence of multi-layer conductive substrates. In certain embodiments, the resulting accuracy and CPU time reduction are a result of a Green's function approach with the correct quasi-static limit, a modified discrete complex image approximation to the Green's function, and a continuous dipole expansion to evaluate the magnetic vector potential at the distances relevant to VLSI interconnects and intentional inductors.
1. One or more computer-readable storage media storing computer-executable instructions which when executed by a computer cause the computer to perform a method, the method comprising:
receiving semiconductor chip design information, the semiconductor chip design information comprising substrate profile information indicating electrical characteristics of a multi-layer substrate over or under which a circuit design is to be implemented;
computing parameters for an approximation of the multi-layer substrate's contribution to a Green's function at one or more frequencies of interest;
generating a representation of the multi-layer substrate's contribution to the Green's function using the computed parameters;
computing impedance values for signal-wire segments in the circuit design using the representation of the multi-layer substrate's contribution to the Green's function; and
outputting the impedance values.
2. The one or more computer-readable media of claim 1 , wherein the outputting comprises storing the impedance values in computer memory or storage.
3. The one or more computer-readable media of claim 1 , wherein the signal-wire segments in the circuit design comprise signal-wire segments for an intentional inductor.
4. The one or more computer-readable media of claim 1 , wherein the act of computing parameters for the approximation of the multi-layer substrate's contribution to the Green's function is performed for a plurality of frequencies of interest.
5. The one or more computer-readable media of claim 1 , wherein the act of computing the parameters comprises fitting a non-linear least squares problem.
6. The one or more computer-readable media of claim 1 , wherein the act of computing the parameters comprises using a variable projection technique.
7. The one or more computer-readable media of claim 1 , wherein the method further comprises receiving circuit design information comprising information indicative of a geometric layout of at least signal-wire segments and ground-wire segments in the circuit design.
8. The one or more computer-readable media of claim 7 , wherein the circuit design is a first circuit design, wherein the circuit design information is first circuit design information, wherein the geometric layout is a first geometric layout, and wherein the method further comprises:
receiving second circuit design information, the second circuit design information comprising information indicative of a second geometric layout of at least signal-wire segments and ground-wire segments in a second circuit design; and
reusing the parameters for the approximation of the multi-layer substrate's contribution to the Green's function to compute impedance values for the signal-wire segments in the second circuit design.
9. The one or more computer-readable media of claim 1 , wherein the method further comprises modifying the circuit design based at least in part on the computed impedance values.
10. The one or more computer-readable media of claim 1 , wherein the outputting comprises generating a netlist representative of electrical characteristics of the circuit design, the netlist including the impedance values.
11. The one or more computer-readable media of claim 10 , wherein the circuit design comprises an intentional inductor, and wherein the netlist comprises information about a resistance part and a reactance part of the electrical characteristics exhibited by the intentional inductor.
12. The one or more computer-readable media of claim 1 , wherein the impedance values comprise mutual impedance values and self impedance values.
13. A method, comprising:
with a computer,
receiving semiconductor chip design information, the semiconductor chip design information comprising substrate profile information indicating electrical characteristics of a multi-layer substrate over or under which a circuit design is to be implemented;
computing parameters for an approximation of the multi-layer substrate's contribution to a Green's function at one or more frequencies of interest;
generating a representation of the multi-layer substrate's contribution to the Green's function using the computed parameters;
computing impedance values for signal-wire segments in the circuit design using the representation of the multi-layer substrate's contribution to the Green's function; and
outputting the impedance values.
14. The method of claim 13 , wherein the outputting comprises storing the impedance values in computer memory or storage.
15. The method of claim 13 , wherein the signal-wire segments in the circuit design comprise signal-wire segments for an intentional inductor.
16. The method of claim 13 , wherein the act of computing parameters for the approximation of the multi-layer substrate's contribution to the Green's function is performed for a plurality of frequencies of interest.
17. The method of claim 13 , wherein the act of computing the parameters comprises fitting a non-linear least squares problem.
18. The method of claim 13 , wherein the act of computing the parameters comprises using a variable projection technique.
19. The method of claim 13 , further comprising receiving circuit design information comprising information indicative of a geometric layout of at least signal-wire segments and ground-wire segments in the circuit design.
20. The method of claim 19 , wherein the circuit design is a first circuit design, wherein the circuit design information is first circuit design information, wherein the geometric layout is a first geometric layout, and wherein the method further comprises:
receiving second circuit design information, the second circuit design information comprising information indicative of a second geometric layout of at least signal-wire segments and ground-wire segments in a second circuit design; and
reusing the parameters for the approximation of the multi-layer substrate's contribution to the Green's function to compute impedance values for the signal-wire segments in the second circuit design.
21. The method of claim 13 , further comprising modifying the circuit design based at least in part on the computed impedance values.
22. The method of claim 13 , wherein the outputting comprises generating a netlist representative of electrical characteristics of the circuit design, the netlist including the impedance values.
23. The method of claim 22 , wherein the circuit design comprises an intentional inductor, and wherein the netlist comprises information about a resistance part and a reactance part of the electrical characteristics exhibited by the intentional inductor.
24. The method of claim 13 , wherein the impedance values comprise mutual impedance values and self impedance values.