Use of breakouts in printed circuit board designs
View Patent ↗An escape outline is provided to automatically identify escape traces of a breakout. Further, the escape outline can be used to associate desired properties with the identified escape traces and allows special behavior of the automatic and interactive routing routines that operate on the escapes. Still further, an escape outline may be employed to improve the creation of escape traces by automatic routing tools. The use of pseudo-pins for netline optimization also is provided. Breakouts in a printed circuit board design are analyzed, and their respective endpoints are identified. These endpoints are then employed in a netline optimization analysis instead of the pins from which the breakouts originate. In this manner, the endpoints of the breakout are used as pseudo-pins to substitute for the actual pins of a component. Because the netline optimization will then be predicated upon the breakout endpoints rather that the originating pins, the pin configuration will be revised to simplify routing to the breakouts.
1. A computer-implemented method of swapping pins in a printed circuit board design, comprising:
identifying traces that extend from a pin of a component object in the printed circuit board design and intersect a perimeter of an escape outline affiliated with the component object as breakouts;
identifying endpoints of the breakouts; and
providing the identified endpoints to a pin-swapping tool for use in a netline optimization process.
2. The computer-implemented method recited in claim 1 , further comprising identifying the endpoints of the breakouts as the intersections of the traces of the breakouts with the perimeter of the escape outline affiliated with the component object.
3. The computer-implemented method recited in claim 1 , further comprising:
creating a map of pins of the component object including the pseudo-pins corresponding to the breakout endpoints;
creating netlines extending from the pseudo-pins; and
performing a netline optimization process using the netlines extending from the pseudo-pins.
4. The computer-implemented method recited in claim 3 , further comprising:
identifying two pseudo-pins to be swapped based upon the netline optimization process using the netlines extending from the pseudo-pins; and
swapping actual pins of the component object corresponding to two identified pseudo-pins to be swapped.
5. A computer-readable storage medium, having a sequence of program instructions stored thereon that are executable by a computer system to perform the method of any claims 1 and 2 - 4 .
6. A pseudo-pin mapping tool, comprising:
a breakout identification module configured to identify breakouts extending from a pin of a component object in the printed circuit board design; and
a breakout endpoint determination module configured to, for each identified breakout,
identify an endpoint of the breakout; and
provide the identified endpoint to a pin-swapping tool for use in a netline optimization process.
7. The pseudo-pin mapping tool recited in claim 6 , further comprising:
a pin-swapping module configured to
create a map of pins of the component object using pseudo-pins corresponding to the breakout endpoints;
create netlines extending from the pseudo-pins; and
perform a netline optimization process using the netlines extending from the pseudo-pins.
8. The pseudo-pin mapping tool recited in claim 7 , wherein the pin-swapping module is further configured to
identify two pseudo-pins to be swapped based upon the netline optimization process using the netlines extending from the pseudo-pins; and
swap actual pins of the component object corresponding to two identified pseudo-pins to be swapped.