Synthesis strategies based on the appropriate use of inductance effects
View Patent ↗A method of optimizing the signal propagation speed on a wiring layout is provided. In general, the method accounts for and uses inductance effects caused by the propagation of a high-speed signal on a signal wire surrounded by parallel ground wires. In particular, one of the physical parameters defining the wiring layout may be adjusted to create an rlc relationship in the wiring layout that maximizes the signal propagation speed. The physical parameter that is adjusted may be, for example, the wire separation between the signal wire and the ground wires or the width of the ground wires. The disclosed method may also be applied to a wiring layout having multiple branches, such as a clock tree. In this context, a first branch may be optimized using the disclosed method. Downstream branches may then be adjusted so that the impedances at the junction between the branches are substantially equal.
1. A computer-implemented method for determining inductance, comprising:
selecting a signal wire and a neighboring ground wire in a design of a wiring layout;
partitioning the wider of either the signal wire or the ground wire into segments having widths substantially equal to the width of the narrower of the signal wire or the ground wire, the partitioning creating a remainder portion;
using a computer, calculating a mutual inductance between the narrower of the signal wire or the ground wire and the segments;
designating the remainder portion as the narrower of the signal wire or the ground wire; and
recursively repeating the partitioning, calculating, and designating until an inductance contribution from the remained portion negligible.
2. The computer-implemented method of claim 1 , wherein the recursive repeating is performed to a recursion depth of four.
3. The computer-implemented method of claim 1 , wherein the calculating includes calculating a geometric mean distance between the signal wire and at least a portion of the segments.
4. A wiring layout having multiple branches, wherein a branch of the wiring layout has an inductance calculated by the computer-implemented method of claim 1 .
5. The computer-implemented method of claim 1 , wherein the method is performed as part of computing an rlc relationship that produces a selected time delay for signal propagation along the signal wire.