IP Library Granted Patent US 8,205,175
Granted Patent B2
US 8,205,175 · App. 11/877,599 · Granted Jun 19, 2012

Structured algorithmic programming language approach to system design

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Quick Facts
Patent No.
US 8,205,175
App. No.
11/877,599
Granted
Jun 19, 2012
Kind
B2
Abstract

An algorithmic programming language approach to system design enables design, synthesis, and validation of structured, system-level specifications, and integrates system-level design into the rest of the design process. The algorithmic programming language design approach includes various techniques and tools, which can be used in combination or independently. For example, the design approach includes techniques and tools for simplifying specification of a design unit interface in a programming language specification and/or simplifying specification of synchronization and sub-design unit concurrency for a design unit. According to a first aspect of the design approach, design occurs at the algorithmic level of abstraction. According to a second aspect, the design approach leverages existing simulation technology for validation at various stages of the design flow. According to a third aspect, a design tool synthesizes a structured, programming language specification into a lower-level specification, such as a VHDL specification.

Claims (28)

1. A non-transitory computer readable storage medium storing computer executable instructions for causing a computer system programmed thereby to perform a method of transforming a programming language specification into a lower-level hardware description language specification, the method comprising:

accepting a programming language specification, the programming language specification including an interface; and

based upon a set of transformation rules, transforming plural methods of the interface into plural ports of a port map of a lower-level hardware description language specification of a design unit.

2. The computer readable storage medium of claim 1 wherein the method further comprises:

transforming an algorithmic method implementation of the programming language specification into a synchronized process of the lower-level hardware description language specification.

3. The computer readable storage medium of claim 1 wherein the transforming the interface further includes:

transforming each of zero or more input methods into an input port of the port map; and

transforming each of zero or more output methods into an output port of the port map.

4. The computer readable storage medium of claim 1 wherein a method of the interface includes as a parameter a pointer to a shared variable, wherein the shared variable is for modeling inout behavior.

5. The computer readable storage medium of claim 1 wherein the method further comprises:

transforming plural native programming language data types into hardware description language data types.

6. The computer readable storage medium of claim 1 wherein the programming language specification includes one or more values specified in a template, the programming language specification being based upon the template.

7. The computer readable storage medium of claim 1 wherein the programming language specification is for a system including hardware and software.

8. The computer readable storage medium of claim 1 wherein the programming language specification includes a C++ class description.

9. A computer readable storage medium storing the lower-level hardware description language specification of claim 1 .

10. A method implemented by a computer, comprising:

accepting a programming language specification, the programming language specification including an interface; and

with the computer and based upon a set of transformation rules, transforming plural methods of the interface into plural ports of a port map of a lower-level hardware description language specification of a design unit.

11. The method of claim 10 wherein the method further comprises:

transforming an algorithmic method implementation of the programming language specification into a synchronized process of the lower-level hardware description language specification.

12. The method of claim 10 wherein the transforming the interface further includes:

transforming each of zero or more input methods into an input port of the port map; and

transforming each of zero or more output methods into an output port of the port map.

13. The method of claim 10 wherein the interface includes as a parameter a pointer to a shared variable, wherein the shared variable is for modeling inout behavior.

14. The method of claim 10 further comprising transforming plural native programming language data types into hardware description language data types.

15. The method of claim 10 wherein the programming language specification includes one or more values specified in a template, the programming language specification being based upon the template.

16. The method of claim 10 wherein the programming language specification is for a system including hardware and software.

17. The method of claim 10 wherein the programming language specification includes a C++ class description.

Assignments (4)
MERGER AND CHANGE OF NAME Recorded Jun 29, 2021
From: MENTOR GRAPHICS CORPORATION; SIEMENS INDUSTRY SOFTWARE INC.
To: SIEMENS INDUSTRY SOFTWARE INC.
Reel/Frame 056702/0387 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 13, 2018
From: CALYPTO DESIGN SYSTEMS, INC.
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 047766/0077 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 21, 2011
From: MENTOR GRAPHICS CORPORATION
To: CALYPTO DESIGN SYSTEMS, INC.
Reel/Frame 027428/0867 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 25, 2007
From: WATERS, SIMON J.; GUTBERLET, PETER P.; TAKACH, ANDRES R.
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 020013/0872 →