Granted Patent
Utility
US 6,515,921
· Confirmation No. 8177
SEMICONDUCTOR STORAGE DEVICE HAVING REDUNDANCY CIRCUIT FOR REPLACEMENT OF DEFECT CELLS UNDER TESTS
Inventor:
Yasuji Koshikawa
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⬇ PDF
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2002-04-23 | TRNA |
Transmittal of New Application | 5 | View | |
| 2002-04-23 | A.PE |
Preliminary Amendment | 4 | View | |
| 2002-04-23 | SPEC |
Specification | 33 | View | |
| 2002-04-23 | CLM |
Claims | 5 | View | |
| 2002-04-23 | ABST |
Abstract | 1 | View | |
| 2002-04-23 | DRW |
Drawings-only black and white line drawings | 9 | View | |
| 2002-04-23 | OATH |
Oath or Declaration filed | 2 | View |
Inventors
Yasuji Koshikawa
Tokyo, JAPAN
Attorneys & Agents of Record
Classification
USPC
365/200
G11C29/00
G11C29/72
G11C29/40
Prosecution
- Examiner
- TRAN, MICHAEL THANH
- Art Unit
- 2818
- Customer No.
- 27667
- Docket No.
- NEC OSP-9931 DIV
- Confirmation No.
- 8177
Foreign Priority
11-368427
·
1999-12-24
·
JAPAN
2000-087458
·
2000-03-27
·
JAPAN
Publication
- Pub. No.
- US20020122343A1
- Pub. Date
- 2002-09-05
Patent Term Adjustment
-117days
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2018-08-21
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2006-11-26
from
NEC CORPORATION
TRANSFER OF 50% INTEREST; ORIGINAL ASSIGNEE RETAINS 50% INTEREST.
Recorded 2003-02-10
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Quick Facts
- Patent No.
- US 6,515,921
- App. No.
- 10/128,015
- Filed
- 2002-04-23
- Granted
- 2003-02-04
- Pub. No.
- US20020122343A1
- Examiner
- TRAN, MICHAEL THANH
- Art Unit
- 2818
- PTA
- -117 days
External Links