Multiple synthesized clocks with fractional PPM control from a single clock source
View Patent ↗A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases.
1. A system for generating multiple synthesized clocks, comprising:
an input terminal for receiving a reference signal;
a phase locked loop circuit configured to generate a plurality of signals that are frequency locked to said reference signal and that have a plurality of different phases; and
a phase rotator coupled to said phase locked loop circuit, said phase rotator configured to (1) assign a relative weighting to said signals from said phase lock loop circuit to form a plurality of weighted signals, and (2) combine said weighted signals to form an output signal, wherein said relative weighting determines an output phase of said output signal.
2. The system of claim 1 , further comprising an additional phase rotator coupled to said output of said phase locked loop circuit and configured to receive said plurality of signals from said phase lock loop circuit.
3. The system of claim 1 , wherein said phase locked loop circuit further comprises:
a phase detector coupled to said input terminal;
a charge pump coupled to an output terminal of said phase detector;
a low pass filter coupled to an output of said charge pump;
a voltage controlled oscillator coupled to an output of said low pass filter;
a divider circuit coupled between an output of said voltage controlled oscillator and a second input of said phase detector.
4. The system of claim 3 , wherein said voltage controlled oscillator further comprises a plurality of delay buffers configured to generate said plurality of output signals having said plurality of phases.
5. The system of claim 4 , wherein said voltage controlled oscillator comprises eight delay cells.
6. The system of claim 3 , wherein a voltage controlled oscillator frequency is a multiple of a frequency of said reference signal, said multiple determined by said divider circuit.
7. The system of claim 1 , wherein said phase rotator is coupled with a logic control unit, wherein said logic control unit controls a rotation speed of said phase rotator.
8. The system of claim 7 , wherein said logic control unit further comprises
a logic control circuit;
a counter for receiving bit counts from said logic control circuit;
a decoder coupled to said counter to decode said bit counts to generate an output count;
a latch coupled to said decoder and said phase rotator, wherein said latch detects said output count and transfers said output count to said phase rotator.
9. The system of claim 8 , wherein said logic control circuit is coupled to parts per million (“PPM”) input terminal, wherein said PPM input terminal supplies a PPM input count to said logic control circuit comprising:
a count accumulator, wherein said count accumulator supplies said bit counts to said counter; and,
a sign latch, wherein said sign latch increases or decreases said bit counts.
10. The system of claim 9 , further comprising an additional phase rotator coupled to said phase locked loop circuit and said additional phase rotator further comprises an additional logic control circuit coupled to an additional PPM input terminal.
11. The system of claim 1 , wherein said phase rotator produces sixty four phases from eight phases generated by said phase locked loop circuit.
12. The system of claim 1 , wherein said phase rotator produces 128 phases from eight phases generated by said phase locked loop circuit.
13. The system of claim 8 , wherein said counter is a six bit counter.
14. The system of claim 8 , wherein said decoder decodes six bits of data into sixty four bits of data.
15. The system of claim 1 , said phase rotator including:
a plurality of differential amplifiers configured to receive said plurality of signals from said phase lock loop, and generate said plurality of weighted signals; and
a plurality of digital to analog converters that selectively provide current for said corresponding differential amplifiers, said digital to analog converters determining said weighting of said weighted signals, and thereby said output phase.
16. The system of claim 15 , further comprising:
a shift register configured to have outputs that control said plurality of digital to analog converters, said shift register continuously shifting one or more bits to control said digital to analog converters, thereby causing a rotation is said output phase of said output signal.